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Feb 12, 2026
Fwd: Webinar Recording: New CLI, OpenFrame & Production
Feb 11, 2026
[C4P] ESSERC 2026
ESSERC 2026 PAPERS SUBMISSION DEADLINE
APRIL 3, 2026
Papers submitted for ESSERC 2026 review must clearly state:
- The purpose of the work
- How and to what extent it advances the state-of-the art
- Specific results and their impact.
Only work that has not been previously published or submitted elsewhere will be considered. Submission of a paper for review and subsequent acceptance is considered as a commitment that the work will not be publicly available prior to the conference. Measurement results or calibration against measured data is required to support the claims of the submitted paper.
ESSERC 2026 Conference Tracks
- Advanced Technology, Process and Materials
- Analog, Power and RF Devices
- Modelling and Simulation of Electron Devices
- Analog Circuits
- Data Converters
- RF & mm‑Wave Circuits
- Frequency Generation Circuits
- Digital Circuits & Systems
- Power Management
- Wireless Systems
- Wireline and Optical Circuits and Systems
- Emerging Computing Devices and Circuits
- Architectures and Circuits for AI and ML
- Devices & Circuits for Sensors, Imagers and Displays
After selection of papers, the authors will be informed about the decision of the Technical Program Committee by e-mail by May 27, 2026.
At the same time, the complete program will be published on the conference website. An oral presentation will be given at the Conference for each accepted paper. No-shows will result in the exclusion of the papers from any conference related publication. The submitted final PDF files must be IEEE Xplore compliant.
Best Paper Award: Papers presented at the conference will be considered for the “Best Paper Award” and “Best Young Scientist Paper Award”. The selection will be based on the results of the paper selection process and the judgment of the conference participants. The award delivery will take place during ESSERC 2027.
For each paper independently, at least one (co-)author is required to register for the conference (one registration one paper policy). Registration fees and deadlines will be available on the conference website.
Feb 10, 2026
Open Silicon microelectronic bootcamp
Call for leaders to organize an Open Silicon microelectronic bootcamp
Bring Chip Design to Your Community!
Join the global Open Silicon movement and gain hands-on experience in chip design and fabrication. Our Q1 2026 bootcamps provide access, mentoring, and real silicon opportunities for students, educators, and innovators.
The IEEE is seeking passionate leaders from around the world to organize microelectronics design bootcamps in their local communities, under the IEEE division 1 OPEN SILICON initiative.
If you organize a bootcamp between February and May 2026, IEEE will sponsor the fabrication of three of your designs. You'll receive your fabricated chips (tape-out) mounted on a development board for testing and hands-on exploration.
Selected bootcamp leaders will be invited to an online training session with Matt Venn (Tiny Tapeout) during the last week of February.
To be considered, please provide the following information at REGISTRATION FORM
Key Dates:
- Bootcamp Leader Registration Deadline: Sunday, February 22nd, 2026
- Leader Training Session: Last week of February (TBD)
- Bootcamp Period: March–May 2026
- Tapeout Submission Deadline: March 23rd, 2026 / May 1st, 2026
- Development Board Shipping: September 2026 / November 2026
Feb 9, 2026
ICMC 2026: Paper Deadline Extended!
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Feb 4, 2026
[C4P] MIXDES 2026
CALL FOR PAPERS
33rd International Conference
MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
25 - 27 June 2026, Poznań, Poland
1. Design of Integrated Circuits and Microsystems
Design methodologies. Digital and analog synthesis. Hardwaresoftware codesign. Reconfigurable hardware. Hardware description languages. Intellectual property-based design. Design reuse.2. Thermal Issues in Microelectronics
Thermal and electro-thermal modelling, simulation methods and tools. Thermal mapping. Thermal protection circuits.3. Analysis and Modelling of ICs and Microsystems
Simulation methods and algorithms. Behavioural modelling with VHDL-AMS and other advanced modelling languages. Microsystems modelling. Model reduction. Parameter identification.4. Microelectronics Technology and Packaging
New microelectronic technologies. Packaging. Sensors and actuators.5. Testing and Reliability
Design for testability and manufacturability. Measurement instruments and techniques.
6. Power Electronics
Design, manufacturing and simulation of power semiconductor devices. Hybrid and monolithic Smart Power circuits. Power integration.
7. Signal Processing
Digital and analogue filters, telecommunication circuits. Neural networks. Fuzzy logic. Low voltage and low power solutions.
8. Embedded Systems
Design, verification and applications.
9. Medical Applications
Medical and biotechnology applications. Biometrics. Thermography in medicine.10. Artificial Intelligence in Electronic SystemsAI-driven design. AI-driven signal and data processing. Edge AI.
Tutorials and Special Sessions Call for Proposals
Several tutorials/special sessions will be held prior to the conference. Authors willing to propose a tutorial at MIXDES 2026 are invited to send a proposal to the Organizing Committee. The proposal should consist of a three-page summary including tutorial title, name and affiliation of the lecturer(s), tutorial objectives and audience, topical outline and provisional schedule of the tutorial.
Enquiries:
Mariusz Orlikowski (Conference Secretary) e-mail: mixdes2026@dmcs.p.lodz.pl
Lodz University of Technology
Department of Microelectronics and Computer Science (K-22)
ul. Wólczańska 221 (building B18)93-005 Łódź, Poland
tel.: +48 604397239
fax: +48 426360327
fax: +48 426360327
[chapter] Compact/SPICE Modeling
Wladek Grabinski and Daniel Tomaszewski
Compact/SPICE Modeling
In: Rudan, M., Brunetti, R., Reggiani, S. (eds)
Springer Handbook of Semiconductor Devices
DOI 10.1007/978-3-030-79827-7_34
Abstract: The microelectronics and nano-electronics industry strongly relies on compact models to reduce a new microelectronic product development costs. The goals of this review are to highlight critical issues for the development of compact models for microelectronics and nano-electronics. In this chapter, we’ve covered the main principles of the compact device modeling. Also discussed are the possibilities of integrating compact models into circuit simulation and design tools, with an emphasis on the Verilog-A standardization, which simplify model implementation into EDA tool.
Feb 2, 2026
[paper] dual metal InAs-GaSb VTFETs
M. Saravanan, Eswaran Parthasarathy, Shiromani Balmukund Rahi and Ramkumar Natarajan
Impact of drain and source engineering on dual metal InAs-GaSb VTFETs
with high-K gate stack design
with high-K gate stack design
Sci Rep 15, 44796 (2025) DOI: 10.1038/s41598-025-28448-x
Department of Electronics and Communication Engineering, SRM Institute of Science and Technology, Kattankulathur, 603203, India
University School of Information and Communication Technology, Gautam Buddha University, Greater Noida, 201312, Uttar Pradesh, India
Department of Electronics and Communication Engineering, SR University, Warangal, 506371, Telangana, India
Abstract: The performance of a Dual-Metal-InAs-GaSb Vertical Tunnel Field Effect Transistor (DM-InAs-GaSb VTFET) with an InAs source pocket was investigated in relation to the gate dielectric materials. This research chose gate dielectric materials such as SiO2, Al2O3, HfO2, and ZrO2. The simulation is performed using the Silvaco Technology Computer-Aided Design (TCAD) software. The drain current (ION) of the DM-InAs-GaSb VTFET, which includes an InAs source pocket and an extended drain, is assessed across several dielectric materials; still, ZrO2 (7.92 × 10− 5 A/µm) and HfO2 (8.15 × 10− 5 A/µm) demonstrate enhanced performance. The transconductance (gm) values were 606 µS/µm for HfO2 and 589 µS/µm for ZrO2. A comparison is performed between the Ge-Si VTFET and the suggested configuration. The proposed DM-InAs-GaSb VTFET demonstrates a 1.5-times increase in ON current (ION) and a three-time boost in transconductance (gm). The frequency response of the proposed device was evaluated by employing its SPICE characteristics to construct the common source amplifier in the SPICE circuit simulator. This amplifier comparison reveals that ZrO2 and HfO2 insulators provide significant gain, with HfO2 displaying a cut-off frequency of 1.808 GHz.
FIG: Cross-sectional schematic (a) DM-InAs-GaSb VTFET with split drain (Device-A),
(b) DM-InAs-GaSb VTFET with reduced channel (Device-B),
(c) DM-InAs-GaSb VTFET with drain extension (Device-C).
(b) DM-InAs-GaSb VTFET with reduced channel (Device-B),
(c) DM-InAs-GaSb VTFET with drain extension (Device-C).
Acknowledgements: The authors acknowledge the SRM Institute of Science and Technology, Kattankulathur, Chennai, India for providing the support and facility to carry out this research work.
ISHI-kai OpenMPW
ISHI-kai (Inter-linked Society on Homemade IC Kai)
https://ishikai.connpass.com/event/382637/
The name was conceived from a society community (association) that deals with open (democratized) silicon semiconductor (ASIC/LSI/IC) and connects various R&D fields.
OpenMPW (Open Multi Project Wafer), which appeared as a pioneer of this, is a shuttle program born with Google's investment in Efabless, and is open and free of charge for semiconductors (ASIC/LSI/ICs), including the tools necessary for making semiconductors (ASIC/LSI/IC) to ISHI manufacturing in the fab. IC). This is exactly the "openness of semiconductors (ASIC/LSI/IC) and EDA/PDK" of the open source movement (democratization of software) that started with GNU! [read more...]
| Time | Title | Speakers | Contents |
|---|---|---|---|
| 20:00 - 20:30 | End-to-end open-source Digital IC Design Participation Report | @jun1okamura/OpenSUSI | - |
| 20:30 - 21:00 | Various event reports such as academic conferences | @nishizawa#2174 | - |
| 21:00 - 21:30 | I thought about the application of self-made LSIs that are no longer a niche | Yuuki Umeta/Newcomer | Although the base of self-made LSIs is expanding, there are still aspects that are established by public subsidies and donations from major companies. Therefore, it cannot be said that there is an established business model (with long-term financial sustainability). I thought it would be a hint for many people, so I thought about how to apply it like brainstorming. |
| 21:30 - 22:00 | The Game Participation Experience Report | @reodon | - |
| 22:00 - 22:30 | About the AX1001 SoC for SWEST27 Robots & IoT Edge | Susumu Yamazaki/SWEST27 Executive Committee & Associate Professor, Kitakyushu City University | This is a lecture given by Mr. Takeoka of Axe Co., Ltd. in SWEST27. The AX1001, a proprietary SoC developed for robots and IoT edges, is equipped with the ROS2rapper IP, which is a completely hardware-based ROS2 communication unit. At the same time, it is also equipped with a "Shochiku V" CPU that is an independent expansion of RISC-V. Shochiku V has multi-threaded control and semaphore by hardware, and realizes RTOS-equivalent functions only with hardware. Shochiku V also has an 8-bit floating-point vector arithmetic mechanism for ML and a Lisp/Prolog acceleration instruction. |
| 22:30 - 23:00 | Launch report of the ISHI Kai's GPS system on the Kagoshima rocket | @noritsuna | We will have the GPS system for rockets being created by the ISHI Association installed on the Kagoshima rocket and participate in the launch experiment. Therefore, we will report on the GPS system and the work of the rocket until the launch and the launch itself. |
| 23:00 - | Chat Corner | Everyone | - |
ToM2026 – XX Year
Topics on Microelectronics
(ToM2026) – XX Year
Università degli Studi di Milano-Bicocca
Italian National Ph.D. Program in Micro- and Nano-Electronics
Updated information: www.mbtechnoservices.com
Directors: Andrea Baschirotto & Piero Malcovati
On the occasion of the twentieth anniversary of the “Topics on Microelectronics” Courses and in consideration of the collaboration with the National Ph.D. Program in Micro- and Nano-Electronics, the Chips-IT Foundation, and IEEE-SSCS Italy, this year the first course will be held in Torre dell'Orso, Puglia, in a setting designed to bring together instructors and participants in an environment of outstanding natural beauty. The second course will be held at the more familiar venue of the University of Milan-Bicocca.
For both courses, the format remains consistent, comprising 15 lessons of 3 hours each, delivered by recognized experts in the field of Microelectronics from both academia and research, as well as from industry. Additionally, the courses are characterized by a strong multidisciplinary approach, due to the dense nature of the covered topics. This choice is motivated by the goal of providing an increasingly broad-based preparation for Ph.D. students.
Finally, it is an honor to complement the first ToM course of the twentieth year with a lecture by Professor Pieter Harpe, who serves as a Distinguished Lecturer for IEEE-SSCS, as part of the activities of the SSCS Italian Chapter.
IEEE-SSCS Distinguished Lecture Program
Monday, June 8, 2026 – 09:00–12:00 P. Harpe (Eindhoven University of Technology)
“ADC Innovations for Improved Resolution, Power and Form Factor”
“Ultra low power SAR ADCs and versatile, dynamic sensor interfaces”
ToM2026/1 – Course Program (June 8–10, 2026)
Venue: Hotel Belvedere, Torre dell'Orso – Melendugno (LE), Italy
Monday, June 8, 2026
16:00–19:00 D. M. Mattes (University of Milan-Bicocca, Italy)
“Analog Design in 7nm-CMOS-FinFET”
Tuesday, June 9, 2026
09:00–12:00 G. Frattini (Analog Devices, Italy)
“What does it take to build a System-In-Package with HV galvanic isolation”
16:00–19:00 C. Forzan (STMicroelectronics, Italy)
“Digital Design Flow: a Journey from Synthesis to Signoff”
Wednesday, June 10, 2026
09:00–12:00 L. Pilotto (ChipsIT Foundation, Italy)
“Introduction to Sub-THz Circuit Design”
16:00–19:00 P. Malcovati (University of Pavia, Italy)
“MEMS and Integrated Microsystems: From Fabrication to Interface Circuits”
ToM2026/2 – Course Program (October 12–14, 2026)
Venue: University of Milan-Bicocca, ItalyMonday, October 12, 2026
14:00–17:00 Q. Li (TU Hamburg, Germany)
“High-Resolution SAR ADC with closed loop time-domain comparison”
Tuesday, October 13, 2026
09:00–12:30 E. Sacchi (Cadence, Italy)
“Electromagnetics in RFICs and RF systems design”
14:00–17:30 M. Demicheli (ChipsIT Foundation, Italy)
“DC-DC conversion techniques”
Wednesday, October 14, 2026
09:00–12:30 M. Sampietro (Polytechnic of Milan, Italy)
“Fighting against electronic noise: how to reach attoAmpere signal detection”
14:00–17:30 M. Chiabrera (Inventvm, Italy)
“Technique and challenges in low latency – low power audio digital design”
are available at www.mbtechnoservices.com
Jan 30, 2026
[report] OpenSUSI Open Source Ecosystem in Japan
Jun Okamura
Open Source Ecosystem in Japan, New OSS Design Activities
IEEE Solid-State Circuits Magazine (Winter 2025)
DOI: 10.1109/MSSC.2025.3634946
The Open Source Utilized Silicon Initiatives (OpenSUSI), established in April 2024 as a nonprofit organization, released an open source 1μm CMOS technology document and the original PDK known as TR-1um [1], on its GitHub repository. The technology was provided by TOKAI RIKA Co., Ltd. [2]. Together with platforms such as SkyWater, GlobalFoundries, and IHP, the availability of such alternative device technologies is vital for the global OSS design community.
On 24–25 September 2025, Kyushu University, TOKAI RIKA, OpenSUSI, and ISHI-Kaian OSS design community in Japan, jointly held a hands-on design seminar using the TR-1-μm open source PDK [read more...]
FIG: (a) and (b) The GDSIIs made by the hands-on design seminar at Kyushu University.
References:
[1] "OpenSUSI/TR-1um" GitHub. [Online]. Available: https://github.com/OpenSUSI/TR-1um
[2] "Tokai Rika" Tokai Rika. [Online]. Available: https://www.tokai-rika.co.jp/en/
[3] "Education Center for Semiconductors and Value Creation" Kyushu University. [Online]. Available: https://ecsvc. ed.kyushu-u.ac.jp/en/index.html
[4] "Security camp 2025 national convention | developing digital talent" IPA (Independent Administrative Agency for Information Processing Promotion). [Online]. Available: https://www.ipa.go.jp/jinzai/security-camp/2025/camp/zenkoku/index.html
[5] R. Brown, "Re: Open letter to the openSUSE Board, project and community (final)," openSUSE Mailing Lists, Jul. 15, 2024. [Online]. Available: https://www. opensusi.org/open-letter
Jan 19, 2026
[mos-ak] [ICMC 2026] Call for Papers!
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