[paper] Threshold Engineering in 2D FETs

Dipanjan Sen, Harikrishnan Ravichandran, Safdar Imam, Subir Ghosh, Krishnendu Mukhopadhyay, Md Yasir Bashir, Thomas S. Ie, Vlastimil Mazanek, Jan Luxa, Chen Chen, Joan M. Redwing, Zdenek Sofer, Shubham Sahay, Mercouri G. Kanatzidis and Saptarshi Das

van der Waals dielectrics for threshold engineering in two-dimensional field effect transistors

Nature Communications (2026)

DOI: 10.1038/s41467-026-69089-6

1. Engineering Science and Mechanics, Penn State University, University Park, PA 16802, USA
2. Department of Chemistry, Northwestern University, Evanston, IL 60208, USA
3. Electrical Engineering, Indian Institute of Technology, Kanpur, India
4. Department of Inorganic Chemistry, University of Chemistry and Technology Prague, CzechRepublic
5. 2DCC, Penn State University, University Park, PA 16802, USA
6. Materials Science and Engineering, Penn State University, University Park, PA 16802, USA
7. Electrical Engineering, Penn State University, University Park, PA 16802, USA

Abstract: Two-dimensional (2D) semiconductors are promising for next-generation field-effect transistors (FETs), but their integration into complementary-metal-oxide-semiconductors (CMOS) logic is hindered by improper threshold voltages (Vth), leading to excessive power consumption. While past efforts have focused on improving electrostatics and near-ideal subthreshold swing (𝑺𝑺), systematic Vth engineering in 2D FETs remains unexplored. Here, we investigate high-κ van der Waals (vdW) dielectrics including metal oxyhalides such as LaOBr, BiOBr, and BiOCl, and bimetallic thiophosphates such as LiInP2S6 (LIPS), LiInP2Se6 (LIPSe) and CuInP2S6 (CIPS) and demonstrate that bimetallic thiophosphates enable programmable and non-volatile Vth tuning in both n-type monolayer MoS₂ and p-type bilayer WSe2 FETs. Leveraging ion-mediated Vth tuning, we realize 2DCMOS inverters with nearly three orders of magnitude reduction in static power while maintaining high switching speed. Combining experiments with industry-compatible SPICE modeling, we identify an optimal Vth window that minimizes power without significant delay penalty, enabling built-in power gating and improved power–performance–area metrics without additional sleep transistors.

Fig: LiInP2S6 as a top-gate dielectric for 2D field-effect transistors (FETs). a) angled scanning electron microscope (SEM) image of dual-gated 2D FET with LiInP2S6(LIPS) as top-gate dielectric and 25 nm thick Al2O3 as the back-gate dielectric. Dual-sweep top-gate transfer characteristic of a b) WSe2 FET obtained by sweeping the VTG from -8 V to 8 V at a constant 𝑉𝐵𝐺 = -4 V and 𝑉𝐷𝑆 = 1 V, both exhibiting a counterclockwise (CCW) hysteresis.

Acknowledgements: SD acknowledges funding support from the National Science Foundation for NSF Career under grant number ECCS-2042154, NSF Fuse, under grant number ECCS-2328741, ONR under grant number N00014-24-1-2565, and ARO under grant number W911NF-23-1-0279. The MOCVDTMD films were grown in the 2D Crystal Consortium–Materials Innovation Platform (2DCC-MIP) facility which is supported by the National Science Foundation under cooperative agreement DMR-2039351. The work at Northwestern was supported in part by the National Science Foundation under award number DMR-2305731. ZS was supported by ERC-CZ program (project LL2101) from the Ministry of Education Youth and Sports (MEYS) and by the project Advanced Functional Nanorobots (reg. No. CZ.02.1.01/0.0/0.0/15_003/0000444 financed by the EFRR). JL was supported by Czech Science Foundation (GACR No. 24-11465S). VM was supported by project LUAUS23049 from Ministry of Education Youth and Sports (MEYS). SS acknowledges the Ministry of Education’s Scheme for Transformational and Advanced Research in Sciences (STARS) Project under Grant MoE-STARS/STARS-2/2023-0023, DST Indo-Korea Research Grant INT/Korea/P-66 under Grant E-47691 and the University Grant Commission, Government of India, through the Senior Research Fellowship, student ID: 200510263123

[paper] Compact IV Model for DG MoS2 FETs

Ahmed Mounir, Francois Lime, Alexander Kloes, Alexandros Provias, Theresia Knobloch, 

K. P. O’Brien, Tibor Grasser and Benjamin Iniguez

Compact I–V Model for Double-Gated MoS2 FETs Including Short-Channel Effects

IEEE TED, Vol. 72, No. 12, Dec 2025

DOI: 10.1109/TED.2025.3622099

Rovira i Virgili University, Tarragona (SP)
THM University of Applied Sciences, Giessen (D)
Technical University of Vienna (A)
Intel Foundry Technology Research, Hillsboro (US)

Abstract: This article presents a physics-based analytical compact model for double-gated molybdenum disulfide (MoS2) field effect transistors (FETs), incorporating key physical and short-channel effects (SCEs), such as mobility degradation and velocity saturation. The model is developed from a unified charge control model by evaluating the charge density within the 2D MoS2 layer, represented using the Lambert W function, which provides an analytical expression valid and continuous from the subthreshold to the above threshold regime. The drain current is then derived from this unified charge control model, and as a function of closed-form equations for the charge densities at the source and drain ends of the channel. Despite its simplicity, the model shows excellent agreement with experimental data for channel lengths down to 60nm, making it a powerful tool for accurately predicting the performance of downscaled devices. By including SCEs, this work extends previous modeling efforts and provides a more comprehensive framework for the simulation and optimization of 2D material-based FETs in circuit design.

FIG: Cross-sectional view of the double-gated MoS2 FET, showing the top gate oxide stack made of Al2O3 and HfO2, with the local back gate oxide consisting of HfO2. Validation of the compact model against experimental data for double-gate MoS2 FET L = 60nm (bottom line)

Acknowledgements: This work was supported in part by European Union Bayesian inference with flexible electronics for biomedical applications (BAYFLEX) under Contract 101099555 and in part by the Ministry of Science of Spain under Contract PID2021122399OB-I00

[paper] TMD FETs

Ahmed Mounir^a, Benjamin Iñiguez^a, François Lime^a, Alexander Kloes^b

Theresia Knobloch^c, Tibor Grasser^c

Compact I-V model for back-gated and double-gated TMD FETs

Solid-State Electronics (2023): 108702

DOI: 10.1016/j.sse.2023.108702

a Rovira I Virgili University, Tarragona, Spain
b University of Applied Sciences, Giessen, Germany
c TU Wien, Vienna, Austria

Abstract: A physics-based analytical DC compact model for double and single gate TMD FETs is presented. The model is developed by calculating the charge density inside the 2D layer which is expressed in terms of the Lambert W function that recently has become the standard in SPICE simulators. The current is then calculated in terms of the charge densities at the drain and source ends of the channel. We validate our model against measurement data for different device structures. A superlinear current increase above certain gate voltage has been observed in some MoS2 FET devices, where we present a new mobility model to account for the observed phenomena. Despite the simplicity of the model, it shows very good agreement with the experimental data.

Fig : 2D schematic structure for 2D TMD FETs: (a) a double gated monolayer MoS2 FET. 

(b) a double gated monolayer WSe2 FET. (c)  single back-gated multilayer MoS2 FET. 

(d) single back-gated monolayer FET.

[book] Device Circuit Co-Design Issues in FETs

Device Circuit Co-Design Issues in FETs

Editors: Shubham Tayal, Billel Smaani, Shiromani Balmukund Rahi, Samir Labiod, Zeinab Ramezani

ISBN 9781032414256280 Pages 269 B/W Illustrations 

August 22, 2023 by CRC Press

Description

This book provides an overview of emerging semiconductor devices and their applications in electronic circuits, which form the foundation of electronic devices. Device Circuit Co-Design Issues in FETs provides readers with a better understanding of the ever-growing field of low-power electronic devices and their applications in the wireless, biosensing, and circuit domains. The book brings researchers and engineers from various disciplines of the VLSI domain together to tackle the emerging challenges in the field of engineering and applications of advanced low-power devices in an effort to improve the performance of these technologies. The chapters examine the challenges and scope of FinFET device circuits, 3D FETs, and advanced FET for circuit applications. The book also discusses low-power memory design, neuromorphic computing, and issues related to thermal reliability. The authors provide a good understanding of device physics and circuits, and discuss transistors based on the new channel/dielectric materials and device architectures to achieve low-power dissipation and ultra-high switching speeds to fulfill the requirements of the semiconductor industry. This book is intended for students, researchers, and professionals in the field of semiconductor devices and nanodevices, as well as those working on device-circuit co-design issues.

Table of Contents

1. Modeling for CMOS Circuit Design. 

2. Conventional CMOS Circuit Design. 

3. Compact modeling of junctionless Gate-All-Around MOSFET for circuit simulation. 

4. Novel Gate-Overlap Tunnel FETs for Superior Analog, Digital, and Ternary Logic Circuit Applications. 

5. Phase Transition Materials for Low Power Electronics. 

6. Impact of total ionizing dose effect on SOI-FinFET with spacer engineering. 

7. Scope and Challenges with Nanosheet FET based Circuit design. 

8. Scope with TFET based Circuit and System Design. 

9. An overview of FinFET based Capacitorless 1T-DRAM. 

10. Literature Review of the SRAM Circuits Design Challenges. 

11.Challenges and Future Scope of Gate-All-Around (GAA) Transistors: 

Physical Insights of Device-Circuit Interactions.