Showing posts with label Engineering. Show all posts
Showing posts with label Engineering. Show all posts

Feb 28, 2026

[paper] Threshold Engineering in 2D FETs

Dipanjan Sen, Harikrishnan Ravichandran, Safdar Imam, Subir Ghosh, Krishnendu Mukhopadhyay, Md Yasir Bashir, Thomas S. Ie, Vlastimil Mazanek, Jan Luxa, Chen Chen, Joan M. Redwing, Zdenek Sofer, Shubham Sahay, Mercouri G. Kanatzidis and Saptarshi Das
van der Waals dielectrics for threshold engineering in two-dimensional field effect transistors
Nature Communications (2026)
DOI: 10.1038/s41467-026-69089-6

1. Engineering Science and Mechanics, Penn State University, University Park, PA 16802, USA
2. Department of Chemistry, Northwestern University, Evanston, IL 60208, USA
3. Electrical Engineering, Indian Institute of Technology, Kanpur, India
4. Department of Inorganic Chemistry, University of Chemistry and Technology Prague, CzechRepublic
5. 2DCC, Penn State University, University Park, PA 16802, USA
6. Materials Science and Engineering, Penn State University, University Park, PA 16802, USA
7. Electrical Engineering, Penn State University, University Park, PA 16802, USA


Abstract: Two-dimensional (2D) semiconductors are promising for next-generation field-effect transistors (FETs), but their integration into complementary-metal-oxide-semiconductors (CMOS) logic is hindered by improper threshold voltages (Vth), leading to excessive power consumption. While past efforts have focused on improving electrostatics and near-ideal subthreshold swing (𝑺𝑺), systematic Vth engineering in 2D FETs remains unexplored. Here, we investigate high-ΞΊ van der Waals (vdW) dielectrics including metal oxyhalides such as LaOBr, BiOBr, and BiOCl, and bimetallic thiophosphates such as LiInP2S6 (LIPS), LiInP2Se6 (LIPSe) and CuInP2S6 (CIPS) and demonstrate that bimetallic thiophosphates enable programmable and non-volatile Vth tuning in both n-type monolayer MoS₂ and p-type bilayer WSe2 FETs. Leveraging ion-mediated Vth tuning, we realize 2DCMOS inverters with nearly three orders of magnitude reduction in static power while maintaining high switching speed. Combining experiments with industry-compatible SPICE modeling, we identify an optimal Vth window that minimizes power without significant delay penalty, enabling built-in power gating and improved power–performance–area metrics without additional sleep transistors.

Fig: LiInP2S6 as a top-gate dielectric for 2D field-effect transistors (FETs). a) angled scanning electron microscope (SEM) image of dual-gated 2D FET with LiInP2S6(LIPS) as top-gate dielectric and 25 nm thick Al2O3 as the back-gate dielectric. Dual-sweep top-gate transfer characteristic of a b) WSe2 FET obtained by sweeping the VTG from -8 V to 8 V at a constant 𝑉𝐡𝐺 = -4 V and 𝑉𝐷𝑆 = 1 V, both exhibiting a counterclockwise (CCW) hysteresis.

Acknowledgements: SD acknowledges funding support from the National Science Foundation for NSF Career under grant number ECCS-2042154, NSF Fuse, under grant number ECCS-2328741, ONR under grant number N00014-24-1-2565, and ARO under grant number W911NF-23-1-0279. The MOCVDTMD films were grown in the 2D Crystal Consortium–Materials Innovation Platform (2DCC-MIP) facility which is supported by the National Science Foundation under cooperative agreement DMR-2039351. The work at Northwestern was supported in part by the National Science Foundation under award number DMR-2305731. ZS was supported by ERC-CZ program (project LL2101) from the Ministry of Education Youth and Sports (MEYS) and by the project Advanced Functional Nanorobots (reg. No. CZ.02.1.01/0.0/0.0/15_003/0000444 financed by the EFRR). JL was supported by Czech Science Foundation (GACR No. 24-11465S). VM was supported by project LUAUS23049 from Ministry of Education Youth and Sports (MEYS). SS acknowledges the Ministry of Education’s Scheme for Transformational and Advanced Research in Sciences (STARS) Project under Grant MoE-STARS/STARS-2/2023-0023, DST Indo-Korea Research Grant INT/Korea/P-66 under Grant E-47691 and the University Grant Commission, Government of India, through the Senior Research Fellowship, student ID: 200510263123

Mar 23, 2021

Virtual Si Museum /2111/ E.Eng Tools

This is how I was introduced to the engineering. My very fist log rule and my HP-21 scientific calculator (successor of the famous HP-35)


REF:
[1] Slide rule: https://en.wikipedia.org/wiki/Slide_rule
[2] HP-21 scientific calculator: https://en.wikipedia.org/wiki/HP-21

Jul 29, 2020

Jerzy Ruzyllo - Guide to Semiconductor Engineering

Guide to Semiconductor Engineering
Jerzy Ruzyllo1 (Pennsylvania State University, USA)
World Scientific Book Series. March 2020
This Guide to Semiconductor Engineering is concerned with semiconductor materials, devices and process technologies which in combination are the driving force behind the unprecedented growth of our technical civilization over the last half a century. This book was conceived and written keeping in mind those who need to learn about semiconductor engineering, who are professionally associated with select aspects of this technical domain and want to see it in a broader context, or are simply interested in semiconductors. In its coverage of semiconductor engineering this Guide departs from textbook-style, monothematic in-depth coverage of topics such as the physics of semiconductors and semiconductor devices, the manufacturing of semiconductor devices and circuits, and the characterization of semiconductor materials. Instead, it covers the entire field of semiconductor engineering in one concise volume with synergistic interactions between various areas clearly identified. It is a holistic approach to the coverage of semiconductor engineering which makes this guide unique among books covering semiconductor related issues available on the market today. 
[Table of Contents]
1Jerzy Ruzyllo is a Distinguished Professor Emeritus in the School of Electrical Engineering and Computer Science at the Pennsylvania State University. He joined Penn State in 1984 after completing his education, obtaining a PhD degree in 1977, and serving on the faculty of the Warsaw University of Technology in Poland. Throughout his career, Dr Ruzyllo was actively involved in research and teaching in the area of semiconductor science and engineering. Dr Ruzyllo is a Life Fellow of IEEE and Fellow of the Electrochemical Society.