3rd MFEM Community Workshop, October 26, 2023

MFEM is a free, open source, lightweight, scalable C++ library for finite element methods.

Features

• Arbitrary high-order finite element meshes and spaces.
• Wide variety of finite element discretization approaches.
• Conforming and nonconforming adaptive mesh refinement.
• Scalable from laptops to GPU-accelerated supercomputers.
• ... and many more.
• See MFEM Gallery, Publications, Videos and News pages.

MFEM is used in many projects, including BLAST, Cardioid, Palace, VisIt, RF-SciDAC, FASTMath, xSDK, and CEED in the Exascale Computing Project.

Annual workshop 

MFEM host an annual workshop and FEM@LLNL seminar series. The MFEM team has  announced the 3rd MFEM Community Workshop, which will take place on October 26, 2023, virtually, using Zoom for videoconferencing. The goal of the workshop is to foster collaboration among all MFEM users and developers, share the latest MFEM features with the broader community, deepen application engagements, and solicit feedback to guide future development directions for the project.

Registration
If you plan to attend, please register no later than October 19th. There is no registration fee. Zoom details will be distributed to participants prior to the event date. For questions, please contact the meeting organizers at mfem@llnl.gov.

[paper] FET Library for VLSI

Taehak Kim¹, Jaehoon Jeong², Seungmin Woo², Jeonggyu Yang¹, Hyunwoo Kim² Ahyeon Nam², Changdong Lee², Jinmin Seo², Minji Kim², Siwon Ryu², Yoonju Oh², and Taigon Song¹,²  

NS3K : A 3nm Nanosheet FET Library for VLSI Prediction in Advanced Nodes 

IEEE ISCAS, 2021, pp. 1-5, DOI 10.1109/ISCAS51556.2021.9401055.

¹School of Electronics Engineering, Kyungpook National University (KNU), Daegu 41566, South Korea
²School of Electronic and Electrical Engineering, Kyungpook National University (KNU), Daegu 41566, South Korea

Abstract: Nanosheet FETs (NSFETs) are expected as future devices that replace FinFETs beyond the 5nm node. Despite the importance of the devices, few studies report the impact of NSFETs in the full-chip level. Therefore, this paper presents NS3K, the first 3nm NSFET library, and presents the results in a full-chip scale. Based on our results, 3nm NSFET reduces power by -27.4%, total wirelength by -25.8%, number of cells by -8.5%, and area by -47.6% over 5nm FinFET, respectively, due to better devices and interconnect scaling. However, careful device/layout designs followed by routing-resource considering standard cells are required to maximize the advantages of 3nm technology. 

Fig: Projected 3nm NSFET library development flow. Upper side of each step shows the names of required tools. Each colored-boxes correspond to the steps required for specific tasks: The blue boxes - device development, the orange boxes - digital design, and the green boxes - back end design, respectively.

Acknowledgements: This research was supported by National R&D Program through the National Research Foundation of Korea (NRF) funded by Ministry of Science and ICT (2020M3H2A1078045). The EDA tool was supported by the IC Design Education Center(IDEC), Korea. This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No.2019R1G1A109470212).