Showing posts with label CM. Show all posts
Showing posts with label CM. Show all posts

Oct 28, 2024

[paper] FOSS support for CM with Verilog-A

Bűrmen, Árpád, Tadej Tuma, Iztok Fajfar, Janez Puhan, Žiga Rojec, Matevž Kunaver
and Sašo Tomažič
Free software support for compact modelling with Verilog-A
Informacije MIDEM 54, no. 4 (October 9, 2024)

Abstract: Verilog-A is the analog subset of Verilog-AMS - a hardware description language for analog and mixed-signal systems. Verilog-A is commonly used for the distribution of compact models of semiconductor devices. For such models to be usable a Verilog-A compiler is required. The compiler converts the model equations into a form that can be used by the simulator. Such compilers have been supplied with commercial simulators for many years now. Free software alternatives are much more scarce and limited in the features they offer. The paper gives an overview of Verilog-A, Free software Verilog-A compilers, and Free software/Open source simulators that can simulate compact models defined in Verilog-A. Advantages and disadvantages of individual compilers and simulators are highlighted.

Tab: Comparison of Free software simulators
Asterisk denotes a feature under development as of Sep. 2024

Acknowledgements: This research was funded in part by the Slovenian Research Agency within the research program ICT4QoL—Information and Communications Technologies for Quality of Life, grant number P2-0246.