[paper] Optoelectronic device library containing multiple Verilog-A models

Guanliang Chen, Zhigang Song and Xinhe Zheng

Optoelectronic device library containing multiple Verilog-A models

Sci Rep 15, 1115 (2025) doi: 10.1038/s41598-024-80150-6

1 Key Laboratory of Solid-State Optoelectronics Information Technology, Institute of Semiconductors, Chinese Academy of Sciences, Beijing, 100083, China
2 Center of Materials Science and Optoelectronics Engineering, University of Chinese Academy of Sciences, Beijing, 100049, China
3 School of Mathematics and Physics, Beijing Key Laboratory for Magneto-Photoelectrical Composite and Interface Science, University of Science and Technology Beijing, Beijing, 100083, China

Abstract: The advancement of the optoelectronic fusion industry has escalated the demands for optoelectronic simulation, yet a comprehensive model library remains unavailable for chip designers. We have utilized the hardware description language Verilog-A to develop an extensive optoelectronic device model library, featuring a full range of device types, unified interfaces, and the capability to simulate the physical effects of devices. Establishing this model library is intended to alleviate the workload of chip designers and reduce development costs.

TAB: Comparison with Verilog-A model library and others

FIG: Schematic diagram of a compact Verilog-A model of VCSEL and its DC test results

[paper] Cryogenic Devices for Quantum Technologies

Jorge Pérez-Bailón, Miguel Tarancón, Santiago Celma, and Carlos Sánchez-Azqueta

Cryogenic Measurement of CMOS Devices for Quantum Technologies

IEEE Transactions on Instrumentation and Measurement (2023)

Quantum Materials and Devices (Q-MAD) Group

Institute of Nanoscience and Materials of Aragón (INMA),

Group of Electronic Design (GDE), University of Zaragoza (SP)

Abstract: In this article we present the experimental characterization of active components of a standard 65nm CMOS technology for a temperature range from 313 to 5K, analyzing the variation of the main parameters over temperature and voltage, recovering their main parameters (threshold voltage Vth, transconductance Gm and channel conductance GDS). The measurement has been carried out wire-bonding the bare dies with the devices to a dedicated printed circuit board (PCB) that has been placed inside a dilution refrigerator. The ID-VDS curves for both NMOS and PMOS transistors shows an increase of ID in the cryogenic regime that is more relevant for high values of VGS because for lower values it is partially compensated by the variation of Vth. Also, a kink is observed in these curves for high VDS values, caused by the bulk current generated by impact ionization at the drain combined with the increased resistivity of the frozen-out substrate. The transconductance Gm reaches non-zero values for higher VGS as T decreases, and then peaks to higher values in the cryogenic regime. In turn, GDS increases for increasing T, following the behavior observed for ID. Both results are in accordance with other thermal characterizations carried out on CMOS transistors in different technologies.

Fig: Detail of the IC in the measurement setup to fit into the cryostat

Aknowlegemetns: This work was supported in part by the Spanish Ministry of Science and Innovation under Grant PID2020-114110RA-I00; and in part by the CSIC Program for the Spanish Recovery, Transformation and Resilience Plan funded by the Recovery and Resilience Facility of the European Union, established by the Regulation (EU) 2020/2094 under Grant 20219PT007