[FOSSDEM 2024] Open PDK Initiative

FOSDEM 2024 was a two-day event organized by volunteers to promote the widespread use of free and open source software. Took place at the ULB Solbosch campus in the beautiful city of Brussels (Belgium), FOSDEM is widely recognized as the best FOSS conference in Europe.

There were two DevRooms to discuss the status and further FOSS CAD/EDA IC design tools developments and open PDK initiative:

• Libre-SOC, FPGA and VLSI DevRoom
• Verilog-AMS in Gnucap
• FOSS CAD/EDA tools supporting the open access PDK initiative
• Open Hardware and CAD/CAM DevRoom
• ngspice circuit simulator - stand-alone and embedded into KiCad

FOSDEM'24 Inauguration Session

VSD Free Webinar - Mixed-signal RISC-V based SoC on FPGA - 23rd July, 7pm IST

 

This 60-min webinar helps you get started with a basic mixed-signal FPGA flow, which can be extended to any complex SoC.VSD and RedwoodEDA conducts 5-day RISC-V based MYTH (Microprocessors for You in Thirty Hours) workshop using transaction level Verilog on Makerchip platform. For people who have done this workshop can use this webinar as an extension to the 5th Day, where RISC-V pipe-lined CPU coded in TL-Verilog is now converted to Verilog language and is a part of a mixed-signal SoC

If you are from ASIC/Physical design back-ground, this webinar will complement your existing work, and you would really get to know similarities and differences between ASIC and FPGA flow, which one is preferred under what conditions and why is it preferred

This single webinar connects VLSI students, analog designers, FPGA designers and ASIC designers. It is also an attempt to bring everyone on the same platform, and serves as a starting point for design verification

Stay tuned for follow-up series of FPGA webinars and 5-day hands-on high intensity FPGA workshop, which will be built around OpenFPGA framework and Makerchip visualization software, that enables the whole community to learn FPGA fundamentals along with labs, without actually having a physical FPGA board.

Agenda:

1. "FPGA on eSim"
   Guest Speaker - Prof. Kannan M Moudgalya, IIT Bombay
2. "chipIgnite Program"
   Guest Speaker - Mike Wishart, CEO eFabless
3. "Tapeout World Program"
   Guest Speaker - Naveed Sherwani, Chairman, OSFPGA
4. "Mixed-signal RISC-V based SoC on FPGA"
   Webinar Instructor - Shivani Shah

Webinar Curriculum:
1) Introduction
2) RVMYTH RISC-V Core
3) Why FPGAs ?
4) TL - Verilog to RTL verilog using Makerchip
5) Functional Simulation using iverilog
6) FPGA - Steps to create project
7) FPGA - Steps to generate IPs
8) FPGA - RTL simulation
9) FPGA - Synthesis
10) FPGA - Implementation and timing analysis
11) FPGA - Bit-stream generation, FPGA programming and ILA
12) Conclusion

Register here (if you don't see the form, please refresh page):
https://lnkd.in/gByg6fZ

[paper] ML based Aging-Aware FPGA Framework

Behnam Ghavami, Milad Ibrahimipour, Zhenman Fang, Lesley Shannon 

MAPLE: A Machine Learning based Aging-Aware FPGA Architecture Exploration Framework

31st International Conference on Field-Programmable Logic and Applications

(FPL 2021 Short Paper),

Virtual Conference, Sept 2021

*Simon Fraser University, Burnaby, BC, Canada

Abstract: In this paper, we develop a framework called MAPLE to enable the aging-aware FPGA architecture exploration. The core idea is to efficiently model the aging-induced delay degradation at the coarse-grained FPGA basic block level using deep neural networks (DNNs). For each type of the FPGA basic block such as LUT and DSP, we first characterize its accurate delay degradation via transistor-level SPICE simulation under a versatile set of aging factors from the FPGA fabric and in-field operation. Then we train one DNN model for each block type to quickly and accurately predict the complex relation between its delay degradation and comprehensive aging factors. Moreover, we integrate our DNN models into the widely used Verilog-to-Routing toolflow (VTR 8) to support analyzing the impact of aging-induced delay degradation on the entire large scale FPGA architecture. Experimental results demonstrate that MAPLE can predict the delay degradation of FPGA blocks 104 to 107 times faster than transistor-level SPICE simulation, with a prediction error less than 0.7%. Our case study demonstrates that FPGA architects can effectively leverage MAPLE to explore better aging-aware FPGA architectures.

Fig: Overview of FPGA fabric and in-field factors affecting FPGA aging at transistor and basic block levels. We use DNNs to model FPGA delay degradation at basic block level.

Acknowledgements: We acknowledge the support from Government of Canada Technology Demonstration Program and MDA Systems Ltd; NSERC Discovery Grant RGPIN-2019-04613 and DGECR 2019-00120; Canada Foundation for Innovation John R. Evans Leaders Fund; Simon Fraser University New Faculty Start-up Grant; Xilinx, Huawei and Nvidia.