[book] Systematic Design of Analog CMOS Circuits

Paul G. A. Jespers, Boris Murmann
Cambridge University Press; 31 Oct 2017; 342pp

Discover a fresh approach to efficient and insight-driven analog integrated circuit design in nanoscale-CMOS with this hands-on guide. Expert authors present a sizing methodology that employs SPICE-generated lookup tables, enabling close agreement between hand analysis and simulation. This enables the exploration of analog circuit tradeoffs using the gm/ID ratio as a central variable in script-based design flows, and eliminates time-consuming iterations in a circuit simulator. Supported by downloadable MATLAB code, and including over forty detailed worked examples, this book will provide professional analog circuit designers, researchers, and graduate students with the theoretical know-how and practical tools needed to acquire a systematic and re-use oriented design style for analog integrated circuits in modern CMOS.

Current state of the art in #modeling heating effects in nanoscale devices - Books - IOPscience https://t.co/E0UlkDDJVk

Current state of the art in #modeling heating effects in nanoscale devices - Books - IOPscience https://t.co/E0UlkDDJVk

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#2D Semiconductor Process and Device Simulator #MicroTec: #modeling Development Status Update... https://t.co/OycWKSCKXj

#2D Semiconductor Process and Device Simulator #MicroTec: #modeling Development Status Update... https://t.co/OycWKSCKXj

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#2D Semiconductor Process and Device Simulator #MicroTec: #modeling Development Status Update… https://t.co/fZy9zm34yX

#2D Semiconductor Process and Device Simulator #MicroTec: #modeling Development Status Update https://t.co/do3ZxocZ5z http://pic.twitter.com/h11HndXXX5

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[paper] Surface Potential Equation for Low Effective Mass Channel Common Double-Gate MOSFET

Ananda Sankar Chakraborty and Santanu Mahapatra, Senior Member, IEEE

in IEEE Transactions on Electron Devices

vol. 64, no. 4, pp. 1519-1527, April 2017

doi: 10.1109/TED.2017.2661798

Abstract: Formulation of accurate yet computationally efficient surface potential equation (SPE) is the fundamental step toward developing compact models for low effective mass channel quantum well MOSFETs. In this paper, we propose a new SPE for such devices considering multisubband electron occupancy and oxide thickness asymmetry. Unlike the previous attempts, here, we adopt purely physical modeling approaches (such as without mixing the solutions from finite and infinite potential wells or using any empirical model parameter), while preserving the mathematical complexity almost at the same level. Gate capacitances calculated from the proposed SPE are shown to be in good agreement with numerical device simulation for wide range of channel thickness, effective mass, oxide thickness asymmetry, and bias voltages [read more...]

FIG: Total gate capacitance per unit width Cgg (Vg) for 7-nm-thick device with 100% asymmetry in front and back oxide thicknesses. nmax = 2. Line = model. Symbol = TCAD

levmar : Levenberg-Marquardt nonlinear least squares algorithms in C/C++

Introduction page: <http://users.ics.forth.gr/~lourakis/levmar/> 

The site provides GPL native ANSI C implementations of the Levenberg-Marquardt optimization algorithm, usable also from C++, Matlab, Perl, Python, Haskell and Tcl and explains their use. Both unconstrained and constrained (under linear equations, inequality and box constraints) Levenberg-Marquardt variants are included. The Levenberg-Marquardt (LM) algorithm is an iterative technique that finds a local minimum of a function that is expressed as the sum of squares of nonlinear functions. It has become a standard technique for nonlinear least-squares problems and can be thought of as a combination of steepest descent and the Gauss-Newton method. When the current solution is far from the correct one, the algorithm behaves like a steepest descent method: slow, but guaranteed to converge. When the current solution is close to the correct solution, it becomes a Gauss-Newton method.

Interfaces for using levmar from high-level programming environments & languages such as Matlab, Perl Python, Haskell and Tcl are also available; please refer to the FAQ for more details.

VALint: the NEEDS Verilog-A Checker

By Xufeng Wang¹, Geoffrey Coram², Colin McAndrew³

1. Purdue University 2. Analog Devices, Inc. 3. Freescale Semiconductor

Version 1.0.0 - published on 31 Mar 2017

doi:10.4231/D3HX15S0V

Abstract: VALint is the NEEDS created, automatic Verilog-A code checker. Its purpose is to check the quality of the Verilog-A code and provide the author feedback if bad practices, common mistakes, pitfalls, or inefficiencies are found. This VALint is published as a standalone tool for the compact model community. It is also built-in as an integrated part of the NEEDS publishing platform [read more...]

[paper] Nanoscale MOSFET Modeling

 Nanoscale MOSFET Modeling: 
Part 1: The Simplified EKV Model for the Design of Low-Power Analog Circuits

C. Enz, F. Chicco and A. Pezzotta

in IEEE Solid-State Circuits Magazine, vol. 9, no. 3, pp. 26-35, Summer 2017

doi: 10.1109/MSSC.2017.2712318

Abstract: This article presents the simplified charge-based Enz-Krummenacher-Vittoz (EKV) [11] metal-oxide-semiconductor field-effect transistor (MOSFET) model and shows that it can be used for advanced complementary metal-oxide-semiconductor (CMOS) processes despite its very few parameters. The concept of an inversion coefficient (IC) is first introduced as an essential design parameter that replaces the overdrive voltage V_G-V_T0 and spans the entire range of operating points from weak via moderate to strong inversion (SI), including the effect of velocity saturation (VS). The simplified model in saturation is then presented and validated for different 40- and 28-nm bulk CMOS processes. A very simple expression of the normalized transconductance in saturation, valid from weak to SI and requiring only the VS parameter mc, is described. The normalized transconductance efficiency G_m/I_D, which is a key figure-of-merit (FoM) for the design of low-power analog circuits, is then derived as a function of IC including the effect of VS. It is then successfully validated from weak to SI with data measured on a 40-nm and two 28-nm bulk CMOS processes. It is then shown that the normalized output conductance G_ds/I_D follows a similar dependence with IC than the normalized G_m/I_D characteristic but with different parameters accounting for drain induced barrier lowering (DIBL). The methodology for extracting the few parameters from the measured I_D-V_G and I_D-V_D characteristics is then detailed. Finally, it is shown that the simplified EKV model can also be used for a fully depleted silicon on insulator (FDSOI) and Fin-FET 28-nm processes [read more...]

FIG: The simplified EKV model applied to a 28-nm FDSOI CMOS process: 

G_m n U_T / I_D versus IC for three different transistor channel lengths

References

[1] A. Bahai, “Ultra-low energy systems: Analog to information,” in Proc. European Solid-State Circ. Conf., Sept. 2016, pp. 3–6.

[2] D. Binkley, Tradeoffs and Optimization in Analog CMOS Design. Hoboken, NJ: Wiley, 2008.

[3] W. Sansen, Analog Design Essentials. New York: Springer-Verlag, 2006.

[4] A. Mangla, M. A. Chalkiadaki, F. Fadhuile, T. Taris, Y. Deval, and C. C. Enz, “Design methodology for ultra low-power analog circuits using next generation BSIM6 MOSFET compact model,” Microelectr. J., vol. 44, no. 7, pp. 570–575, July 2013.

[5] Y. S. Chauhan, S. Venugopalan, M. A. Chalkiadaki, M. A. U. Karim, H. Agarwal, S. Khandelwal, N. Paydavosi, J. P. Duarte, C. C. Enz, A. M. Niknejad, and C. Hu, “BSIM6: Analog and RF compact model for bulk MOSFET,” IEEE Trans. Electron Dev., vol. 61, no. 2, pp. 234–244, Feb. 2014.

[6] C. Enz, M. A. Chalkiadaki, and A. Mangla, “Low-power analog/RF circuit design based on the inversion coefficient,” in Proc. European Solid-State Circ. Conf., Sept. 2015, pp. 202–208.

[7] C. Enz and A. Pezzotta, “Nanoscale MOSFET modeling for the design of low-power analog and RF circuits,” in Proc. Int. Conf. MIXDES, June 2016, pp. 21–26.

[8] W. Sansen, “Analog CMOS from 5 micrometer to 5 nanometer,” in Proc. IEEE Int. Solid State Circuits Conf. Dig. Tech. Papers, Feb. 2015, pp. 1–6.

[9] W. Sansen, “Analog design procedures for channel lengths down to 20 nm,” in Proc. IEEE 20th Int. Conf. Electronics, Circuits, and Systems, Dec. 2013, pp. 337–340.

[10] C. C. Enz and E. A. Vittoz, Charge-Based MOS Transistor Modeling - The EKV Model for Low-Power and RF IC Design. Hoboken, NJ: Wiley, 2006.

[11] C. C. Enz, F. Krummenacher, and E. A. Vittoz, “An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications,” Analog Integr. Circuits Signal Process. J., vol. 8, pp. 83–114, July 1995.

[12] P. Heim, S. R. Schultz, and M. A. Jabri, “Technology-independent biasing technique for CMOS analogue micropower implementations of neural networks,” in Proc. Sixth Australian Conf. Neural Networks, Sydney, Australia, 1995, pp. 9–12.

[13] C. C. Enz and E. A. Vittoz, “CMOS low-power analog circuit design,” in EmergingTechnologies: Designing Low Power Digital Systems, R. Cavin and W. Liu, Eds. Piscataway, NJ: IEEE, 1996, pp. 79–133.

[14] E. Vittoz and J. Fellrath, “CMOS analog integrated circuits based on weak inversion operations,” IEEE J. Solid-State Circuits, vol. 12, no. 3, pp. 224–231, June 1977.

[15] A. Mangla, C. C. Enz, and J. M. Sallese, “Figure-of-merit for optimizing the current efficiency of low-power RF circuits,” in Proc. Int. Conf. Mixed Design Integrated Circuits and Systems, June 2011, pp. 85–89.

[16] A. Mangla, “Modeling nanoscale quasi-ballistic MOS transistors,” Ph.D. dissertation, EPFL, Switzerland, Dissertation No. 6385, 2014.

[17] R. R. Troutman and A. G. Fortino, “Simple model for threshold voltage in a short- channel IGFET,” IEEE Trans. Electron. Dev., vol. 24, no. 10, pp. 1266–1268, Oct. 1977.

[18] N. Arora, MOSFET Models for VLSI Circuit Simulation. New York: Springer-Verlag, 1993.

[19] Z. H. Liu, C. Hu, J. H. Huang, T. Y. Chan, M. C. Jeng, P. K. Ko, and Y. C. Cheng, “Threshold voltage model for deep submicrometer MOSFETs,” IEEE Trans. Electron Dev., vol. 40, no. 1, pp. 86–95, Jan. 1993.

[20] M. A. Chalkiadaki, “Characterization and modeling of nanoscale MOSFET for ultra-low power RF IC design,” Ph.D. dissertation, EPFL, Switzerland, Dissertation No. 7030, 2016.

Physics-Based Multi-Bias RF Large-Signal GaN HEMT #Modeling and Parameter Extraction Flow - IEEE Xplore Document... https://t.co/tT8gOLBa9k

Physics-Based Multi-Bias RF Large-Signal GaN HEMT #Modeling and Parameter Extraction Flow - IEEE Xplore Document... https://t.co/tT8gOLBa9k

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Physics-Based Multi-Bias RF Large-Signal GaN HEMT #Modeling and Parameter Extraction Flow - IEEE Xplore Document… https://t.co/xwC7X2oxYm

Physics-Based Multi-Bias RF Large-Signal GaN HEMT #Modeling and Parameter Extraction Flow - IEEE Xplore Document https://t.co/sds4WvM9TZ http://pic.twitter.com/EmSfD8SUZO

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An Analytical #Model for the Gate C–V Characteristics of UTB III—V-on-Insulator MIS Structure - IEEE Xplore... https://t.co/Fe1Fqwu5BJ

An Analytical #Model for the Gate C–V Characteristics of UTB III—V-on-Insulator MIS Structure - IEEE Xplore... https://t.co/Fe1Fqwu5BJ

— Wladek Grabinski (@wladek60) August 25, 2017

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An Analytical #Model for the Gate C–V Characteristics of UTB III—V-on-Insulator MIS Structure - IEEE Xplore Documen… https://t.co/oeYfcvWNvI

An Analytical #Model for the Gate C–V Characteristics of UTB III—V-on-Insulator MIS Structure - IEEE Xplore Document https://t.co/W0W0Yhy0Ci http://pic.twitter.com/bWq1erxitj

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Modeling and simulation of biological systems using SPICE language

Morgan Madec¹, Christophe Lallement¹, Jacques Haiech²

¹ICube, UMR7357, CNRS / Université de Strasbourg, France

²LIT, UMR 7200, CNRS / Université de Strasbourg, France

Published: August 7, 2017
doi: 10.1371/journal.pone.0182385

Abstract: The article deals with BB-SPICE (SPICE for Biochemical and Biological Systems), an extension of the famous Simulation Program with Integrated Circuit Emphasis (SPICE). BB-SPICE environment is composed of three modules: a new textual and compact description formalism for biological systems, a converter that handles this description and generates the SPICE netlist of the equivalent electronic circuit and NGSPICE which is an open-source SPICE simulator. In addition, the environment provides back and forth interfaces with SBML (System Biology Markup Language), a very common description language used in systems biology. BB-SPICE has been developed in order to bridge the gap between the simulation of biological systems on the one hand and electronics circuits on the other hand. Thus, it is suitable for applications at the interface between both domains, such as development of design tools for synthetic biology and for the virtual prototyping of biosensors and lab-on-chip. Simulation results obtained with BB-SPICE and COPASI (an open-source software used for the simulation of biochemical systems) have been compared on a benchmark of models commonly used in systems biology. Results are in accordance from a quantitative viewpoint but BB-SPICE outclasses COPASI by 1 to 3 orders of magnitude regarding the computation time. Moreover, as our software is based on NGSPICE, it could take profit of incoming updates such as the GPU implementation, of the coupling with powerful analysis and verification tools or of the integration in design automation tools (synthetic biology).

GeNeDA results from the collaboration between three laboratories:
The Laboratory of Engineering Sciences, Computer Sciences and Imaging, ICube, UMR7357, CNRS / Université de Strasbourg, France (Morgan MADEC, Yves GENDRAULT, Elise ROSATI and Christophe LALLEMENT)
The Laboratory of Therapeutic Innovation, LIT, UMR 7200, CNRS / Université de Strasbourg, France (Jacques HAIECH)
The Laboratory of Computer Sciences of Paris 6, LIP6, UMR7606, CNRS / Université Pierre et Marie Curie, Paris, France (François PECHEUX)

Relared papers has been published recently
[1] M. Madec, F. Pêcheux, Y. Gendrault, E. Rosati, C. Lallement and J. Haiech, "GeNeDA: An Open-Source Workflow for Design Automation of Gene Regulatory Networks Inspired from Microelectronics", Journal of Computational Biology, June 2016. doi:10.1089/cmb.2015.0229.
[2] M. Madec et al., "Reuse of Microelectronics Software for Gene Regulatory Networks Design Automation", 1st international conference of the GDB BioSynSys, Paris (FR), Sept. 2016.
[3] M. Madec et al., "EDA inspired Open-source Framework for Synthetic Biology", IEEE 2013 BioCAS Conference, Rotterdam (NL), Nov. 2013.

Germany’s RWTH Aachen University and AMO launch joint Aachen Graphene & 2D-Materials Center

RWTH Aachen University and AMO GmbH in Germany have launched a new joint research center with a focus on efficiently bridging the gap between fundamental science and applications within graphene and related materials-based electronics and photonics.

Sharing the vision of bringing graphene and related materials research from the lab into applications, the five founding principal investigators of the Aachen Graphene and 2D-Materials Center (who are also all members of the EU-funded Graphene Flagship project) are professor Christoph Stampfer (of RWTH, and spokesman for the center), professor Max Lemme (of AMO and RWTH), professor Markus Morgenstern (of RWTH), professor Renato Negra (of RWTH) and Dr Daniel Neumaier (of AMO).

“The center will help to turn the exciting properties of graphene and 2D [two-dimensional] materials into true functions, making these materials not only fascinating for scientists but also serving society,” said Christoph Stampfer following the center’s kick-off meeting on 24 July. “With the Aachen Graphene and 2D-Material Center, we aim at increasing the visibility of Aachen as an excellent place to undertake graphene and 2D material research with both a fundamental and applied focus.”

The center enables the integration of the already ongoing work from RWTH Aachen University and AMO under a legal framework that allows for full collaboration between the groups. In particular, the center will focus on addressing the challenges of future technology including high-frequency electronics, flexible electronics, energy-efficient sensing, photonics as well as spintronics and valleytronics with graphene and related materials and their heterostructures.

Founding Members of the Aachen Graphene and 2D Materials Center:

• Prof. Christoph Stampfer, RWTH Aachen University (Spokesman)
• Prof. Max Lemme, RWTH Aachen University/AMO GmbH
• Prof. Markus Morgenstern , RWTH Aachen University
• Prof. Renato Negra, RWTH Aachen University
• Dr. Daniel Neumaier, AMO GmbH

Performance Assessment of A Novel Vertical Dielectrically Modulated TFET-Based Biosensor - IEEE Xplore #paper https://t.co/jRvJS3MUTs

Performance Assessment of A Novel Vertical Dielectrically Modulated TFET-Based Biosensor - IEEE Xplore #paper https://t.co/jRvJS3MUTs

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A Threshold Voltage #Model of Tri-Gate Junctionless Field-Effect Transistors Including Substrate Bias Effects https://t.co/sEviQXJbB3

A Threshold Voltage #Model of Tri-Gate Junctionless Field-Effect Transistors Including Substrate Bias Effects https://t.co/sEviQXJbB3

— Wladek Grabinski (@wladek60) August 18, 2017

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[paper] Improvements to a compact MOSFET model for design by hand

Improvements to a compact MOSFET model for design by hand

A. de Jesus Costa, F. Martins Cardoso, E. Pinto Santana and A. I. Araújo Cunha

15th IEEE NEWCAS

Strasbourg, France, 2017, pp. 225-228

doi: 10.1109/NEWCAS.2017.8010146

Abstract: In this work, an improved version of the basic structure of a compact MOSFET model and the respective parameters extraction methodology are proposed. The aim of this approach is to increase accuracy in hand calculations for analog circuit design without significantly increasing its complexity. The influences of both inversion level and channel length are considered in the modeling of a few features such as mobility, threshold voltage and onset of saturation. Simple design examples of current sinks and sources are accomplished to compare the basic and the improved models [read more...]

[mos-ak] [Workshop Program] 15th MOS-AK ESSDERC/ESSCIRC Workshop in Leuven Sept.11 2017

15th MOS-AK ESSDERC/ESSCIRC Compact Modeling Workshop

Leuven; Monday Sept.11, 2017 (8:30-17:00)

Workshop Program online http://www.mos-ak.org/leuven_2017/ 

Together with International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) and Jean-Michel Sallese, EPFL (CH), Daniel Tomaszewski, ITE (PL), MOS-AK Technical Program Coordinators as well as all the Extended MOS-AK TPC Members, we have pleasure to invite to the 15th consecutive MOS-AK workshop organized as an integral part of the ESSDERC/ESSCIRC Conferences in Leuven on Sept.11, 2017. The MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to the compact/SPICE modeling and its Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Final Program of 15th MOS-AK ESSDERC/ESSCIC Workshop is available online:

http://www.mos-ak.org/leuven_2017/

Venue: 

KU LEUVEN Campus of Social Sciences 

(Parkstraat 45, 3000 Leuven) 

room AV 91.12

Online MOS-AK/Leuven Workshop Registration:

http://www.esscirc-essderc2017.org/howtoregister

(any related inquiries can be sent to register@mos-ak.org)

The MOS-AK workshop will be followed by four session of the ESSDERC Track4 "Device and Circuit Compact Modeling". These four lecture sessions include one invited and 14 pear reviewed papers in the compact/SPICE modeling and Verilog-A standardization domain:

Tuesday September 12, 2017 (11:00-12:20)

Cross-Domain Compact Modeling  

Chair: Wladek Grabinski - MOS-AK; Cristell Maneux - U-Bordeaux;

Tuesday September 12, 2017 (14:00-15:20)

Parameter Extraction  

Chair: Thierry Poiroux - CEA

Tuesday September 12, 2017 (16:40-18:00)

Modeling of Emerging Devices  

Chair: Jean-Michel Sallese - EPFL; Daniel Tomaszewski - ITE;

Wednesday September 13, 2017 (14:20-15:40)

Traps and Noise  

Chair: Benjamin Iniguez - URV; Sadayuki Yoshitomi - Toshiba;

MOS-AK Postworkshop Publications:

Selected best MOS-AK technical presentation will be recommended for further publication

in a special issue of the International Journal of High Speed Electronics and Systems 

Extended MOS-AK Committee

WG170817

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Review of commercial SiC MOSFET models: Topologies and equations - IEEE Xplore #paper https://t.co/LS090HojeE

Review of commercial SiC MOSFET models: Topologies and equations - IEEE Xplore #paper https://t.co/LS090HojeE

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[paper] Compact Electro-Mechanical-Fluidic Model for Actuated Fluid Flow System

Compact Electro-Mechanical-Fluidic Model for Actuated Fluid Flow System

T. K. Maiti, Member, IEEE, L. Chen, H. Zenitani, H. Miyamoto, Member, IEEE,

M. Miura-Mattausch, Fellow, IEEE, and H. J. Mattausch, Senior Member, IEEE

in IEEE Journal on Multiscale and Multiphysics Computational Techniques, 

vol. 2, no. , pp. 124-133, 2017.

doi: 10.1109/JMMCT.2017.2731878

Abstract: This paper presents a compact electro-mechanical-fluidic system-modeling method for multidomain system simulation based on multidomain physics that considers the total energy conservation condition, in terms of respective potential and flow quantities. Models for electrical, mechanical, and fluidic domains are developed to design the example of a blood pumping system, where the blood flow is driven by electrically controlled organic actuators. The electrical domain includes an organic mosfet-based control circuit, the mechanical domain includes organic actuators, and the fluidic domain includes a flexible fluid-flow channel. Control circuit, actuators, and fluid models are coupled through equivalent circuits, where interconnection relationships between two neighboring domains are expressed using the energy conservation concept. The model accuracy is verified with finite element method (FEM) based numerical simulation. Significantly faster simulation speed than with FEM and good accuracy were achieved [read more...]

TABLE: CORRESPONDING FORCE AND FLOW EQUATIONS FOR ELECTRICAL AND
MECHANICAL DOMAINS ARE SUMMARIZED [21]-[23]

[21] S. D. Senturia, Microsystems Design. Norwell, MA: Kluwer Academic Publisher, 2001.

[22] T. K. Maiti, L. Chen, H. Miyamoto, M. Miura-Mattausch, and H. J. Mattausch, “Modeling of electrostatically actuated fluid flow system for mixed-domain simulation,” in 20th Int. Conf. on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 190-193, Sept. 2015, USA.

[23] T. K. Maiti, L. Chen, H. Miyamoto, M. Miura-Mattausch, and H. J. Mattausch, “Mixed domain compact modeling framework for fluid flow driven by electrostatic organic actuators,” in 45th European Solid-State Device Research Conference (ESSDERC), pp. 52-55, Sept. 2015, Austria. 

A General and Transformable #Model Platform for Emerging Multi-Gate MOSFETs - IEEE Xplore Document https://t.co/q27OgRX5Fd

A General and Transformable #Model Platform for Emerging Multi-Gate MOSFETs - IEEE Xplore Document https://t.co/q27OgRX5Fd

— Wladek Grabinski (@wladek60) August 14, 2017

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Mini-Colloquium (MQ) on Nanoelectronics

AGENDA
DATE: Saturday Aug. 26, 2016

VENUE: IIT Kanpur L16

This Mini-Colloquium (MQ) on Nanoelectronics is being hosted by the IEEE Electron Device Society UP Chapter in collaboration with the Department of Electrical Engineering at IIT Kanpur. Distinguished speakers from renowned universities will be presenting on wide range of topics in Nanoelectronics. The MQ will be organized into 1 hour talks by the speakers. The agenda would be as follows:

Time	Topic	Speaker
9:00 - 9:15	Inauguration
9:15 - 9:30	High Tea
9:30 - 10:30	Nanotransistors with 2D materials: Opportunities and Challenges	Prof. Navkanta Bhat IISc
10:30 - 11:30	Revisiting gate C-V characterization for high mobility semiconductor MOS devices	Prof. Anisul Haque East West Univ.
11:30 - 11:45	Tea
11:45 - 12:45		Prof. V. Ramgopal Rao IIT Delhi
12:45 - 14:15	Lunch
14:15 - 15:15	ASM-HEMT - First Industry Standard Compact Model for GaN HEMTs	Prof. Yogesh Singh Chauhan IIT Kanpur
15:15 - 16:15	Spintronics - Perspectives and Challenges	Prof. Brajesh Kumar Kaushik IIT Roorkee
16:15 - 16:30	Tea
16:30 - 17:30	Advanced Hetero structure based Nano Scale MOSFETs	Prof. Chandan Kumar Sarkar Jadavpur Univ.

Coordinator: Dr. Yogesh S.Chauhan IIT Kanpur, India
Website: http://www.iitk.ac.in/nanolab/MQ/index.html

ICCDCS 2017

Tenth International Caribbean Conference on Devices, Circuits and Systems (ICCDCS 2017)

June 5-7 2017, Cozumel, México

08:00 to 9:00	Registration	Registration	Registration
08:45 to 9:00	Opening Ceremony
09:00 to 10:00	Key Note 1: "Adaptive Heterogenous Multi-Core Technologies- Intelligent, Interconnected and Integrated Cyber-Physical Systems (I3CPS)", Jürgen Becker	Key Note 3: "The Life and Times of Eugeni García", Benjamín Íñiguez	Key Note 6: "On the Extraction Methods for MOSFET Series Resistance and Mobility Degradation using a Single Test Device",Adelmo Ortiz Conde
10:00 to 10:30	Break	Break	Break
10:30 to 12:30	Session 1	Session 3	Session 5
10:30 to 10:50	"Model Based Photopic Electroretinogram Source Separation: A Multiresolution Analysis Approach", Prashanth Chetlur Adithya, Alaql Abdulrahman, Radouil Tzekov, Ravi Sankar and Wilfrido Moreno	"A Programmable CMOS Voltage Controlled Ring Oscillator for Radio-Frequency Diathermy On-chip Circuit", Antonio Corres- Matamoros, Esteban Martinez-Guerrero and Jose E. Rayas-Sanchez	"Health Index Assessment for Power Transformers with Thermal Upgraded Paper up to 230kV, Using Fuzzy Inference. Part II: A Sensibility Analysis", Diego Chacón, Juan Pablo Lata and Ricardo Medina
10:50 to 11:10	"Analytical Model Parameter Determination for Microwave On-Chip Inductors up to the Second Resonant Frequency", José Valdés Rayón, Reydezel Torres and Roberto Murphy	"A logarithmic CMOS image sensor with wide output voltage swing range", Fernando Campos, Mário Bordon, Marcelo Silva and Jacobus Swart	"Implementation Model Using a Hippocratic Protocol in Mobile Terminals with NFC Technology", Carlos Kowalevicz, Jose Pirrone Puma and Monica Huerta
11:10 to 11:30	"Energy Consumption Improvement based on Distance Adaptive Modulation in Optical Elastic Network", Sabi Bandiri, Rafael Braga, Tales Pimenta and Danilo Spadoti	"Improving Magnitude Response in Two-Stage Corrector Comb Structure", Gordana Jovanovic Dolecek and Lyda Herrera Sepulveda	"Internet of Things as an Attack Vector to Critical Infrastructures of Cities", Pablo Leonidas Gallegos-Segovia, Jack Fernando M. Larios-Rosillo and Erwin Jairo Sacoto-Cabrera
11:30 to 11:50	"Switching Region Analysis for SOTB Technology", Carlos Cortes Torres, Nobuyuki Yamasaki and Hideharu Amano	"Analysis of the influence of the buffer layer in the characteristic impedance of electro-optic modulators", Ana Gabriela Correa Mena, Luis Alejandro González Mondragón, Leidy Johana Quinteros Rodríguez, José Valdés Rayón and Ignacio Enrique Zaldívar Huerta	"Sensors for Parkinson's Disease Evaluation", Raquel Torres, Monica Huerta, Ricardo Gonzalez, Roger Clotet and Juan Pablo Bermeo
11:50 to 12:10	"Scalable Models to Represent the Via-Pad Capacitance and Via-Traces Inductance in Multilayer PCB High-Speed Interconnects", Abraham Isidoro Muñoz, Miguel Angel Tlaxcalteco Matus, Reydezel Torres Torres and Gaudencio Hernandez Sosa	"Impact of neglecting the metal losses on the extraction of the relative permittivity from PCB transmission line measurements", Erika Yazmin Teran Bahena and Reydezel Torres Torres	"QoS Evaluation of VPN in a Raspberry Pi devices over Wireless Network", Luis Caldas, Juan Jara and Mónica Huerta
12:10 to 12:30	"Implementation of a Reconfigurable Neural Network in FPGA", Janaina Oliveira, Robson Moreno, Odilon Dutra and Tales Pimenta	"Reconfigurable FIR Filter Coefficient Optimization in Post-Silicon Validation to Improve Eye Diagram for Optical Interconnects",Ismael Duron-Rosales, Francisco E. Rangel-Patino, Jose E. Rayas-Sanchez, Jose L. Chavez-Hurtado and Nagib Hakim	"A Proposed Digital Predistorter Based on NLMS and PSO Algorithms", Omar Alngar, Walid El-Deeb and El-Sayed El-Rabaie
12:30 to 15:00	Lunch	Lunch	Closing remarks
15:00 to 16:00	Key Note 2: "Following the Path of 3D Integration", Malgorzata Chrzanowska-Jeske	Key Note 4: “Modeling and Verification of Heterogeneous Systems”, Filipe Vinci
16:00 to 16:15	Break	Poster Introduction*
16:15 to 17:55	Session 2	Session 4
16:15 to 16:35	"MRAM control Transistor Resilience against Heavy-Ion Impacts", Walter Enrique Calienes Bartra, Raphael Brum, Guilherme Flach and Ricardo Reis	Break w/poster session (16:15 to 17:00)
16:35 to 16:55	"A Charge-controlled Memristor Model for Image Edge Detection with a Memristive Grid", Arturo Sarmiento and Yojanes Rodríguez-Velásquez
16:55 to 17:15	"Characterization and modelling of Ag/TiO2/ITO devices exhibiting bipolar memristive properties", Jesús Jiménez-León, Arturo Sarmiento, Carlos De La Cruz Blas and Cristina Gomez-Polo
17:15 to 17:35	"Assessing the accuracy of the open, short and open-short de-embedding methods for on-chip transmission line s-parameters measurements", Juan Garcia Santos and Reydezel Torres	Key Note 5: (17:00 to 18:00) "Innovation by ASIC design and emerging substream markets"Jacobus Swart
17:35 to 17:55	"Evaluation of Interconnects Based on Electromigration Criteria and Circuit Performance", Rafael Nunes, Roberto Orio and Jacobus Swart
19:00	Welcome Cocktail
19:30		Conference Banquet

Poster Session:

"Differentiated synchronization plus FHIR a solution for EMR's Ecosystem", Roger Clotet, Emilio Hernández and Monica Karel Huerta

"Design and Validation of a Portable Radio-Frequency Diathermy Prototype", Antonio Corres-Matamoros, Esteban Martinez-Guerrero and Jose E. Rayas-Sanchez

"Stimulating social interaction among elderly people through sporadic social networks", Jorge Osmani Ordoñez-Ordoñez, Jack Fernando Bravo-Torres, Oscar David Sari-Villa, Esteban Fernando Ordoñez-Morales, Martín López-Nores and Yolanda Blanco-Fernández

"Sensing Climatic Variables in a Orchid Greenhouse", Luis Fernandez, Mónica Huerta, Giovanni Sagbay, Roger Clotet and Angel Soto

"Low cost system for monitoring physiological signals using FPGA and Android Tablet", J. Bucheli, D. Rivas, J. Gavilema, D. Mullo, J. L. Carrillo, M. Huerta

Basics of MOSFET Modeling

Basics of MOSFET Modeling with LabVIEW/LTspice 

• Introduction to MOSFET Models 
• Functions and Parameter Extraction
• visit http://mosfet-engineer.blogspot.com

[paper] On the Physical Behavior of Cryogenic IV and III-V Schottky Barrier MOSFET Devices

On the Physical Behavior of Cryogenic IV and III–V Schottky Barrier MOSFET Devices

Mike Schwarz, Member, IEEE, Laurie E. Calvet, Member, IEEE, John P. Snyder, Member, IEEE, Tillmann Krauss, Udo Schwalke, Senior Member, IEEE, and Alexander Kloes, Senior Member, IEEE

in IEEE TED , vol.PP, no.99, pp.1-8

doi: 10.1109/TED.2017.2726899

Abstract: The physical influence of temperature down to the cryogenic regime is analyzed in a comprehensive study and the comparison of IV and III-V Schottky barrier (SB) double-gate MOSFETs. The exploration is done using the Synopsys TCAD Sentaurus device simulator and first benchmarked with experimental data. The important device physics of both SB-MOSFETs and conventional MOSFETs are reviewed. The impact of temperature on device performance down to the liquid-nitrogen regime is then explored. We find reduced drive currents in SB-MOSFETs fabricated on small effective mass materials and that SB lowering can significantly improve SB-MOSFETs, especially at low temperatures [read more...]

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination

[paper] Circuit-level simulation methodology for Random Telegraph Noise by using Verilog-AMS

T. Komawaki, M. Yabuuchi, R. Kishida, J. Furuta, T. Matsumoto and K. Kobayashi

Circuit-level simulation methodology for Random Telegraph Noise by using Verilog-AMS

2017 IEEE ICICDT, Austin, TX, USA, 2017, pp. 1-4.

doi: 10.1109/ICICDT.2017.7993526

Abstract: As device sizes are downscaled to nanometer, Random Telegraph Noise (RTN) becomes dominant. It is indespensable to accurately estimate the effect of RTN. We propose the RTN simulation method for analog circuits. It is based on the charge trapping model. We replicate the RTN-induced threshold voltage fluctuation to attach a variable DC voltage source to the gate of MOSFET by using Verilog-AMS. We confirm that drain current of MOSFETs temporally fluctuates. The fluctuations of RTN are different for each MOSFET. Our proposed method can be applied to estimate the temporal impact of RTN including multiple transistors. We can successfully replicate RTN-induced frequency fluctuations in 3-stage ring oscillators as similar as the measurement results [read more...]

Circuit Design and Simulation Project using eSim

Invitation to participate in Circuit Design and Simulation Project using eSim

The FOSSEE (Free and Open Source Software for Education) project based at lIT Bombay has initiated a Circuit Design and Simulation Project using esim (an open source EDA tool for circuit design, simulation, analysis and PCB design).

Interested candidates can take any solved electronic circuit from any source and redesign it using eSim and submit it to us. Candidates will be rewarded with certificates and honorarium after a review process. These circuits will also be published on our website under an appropriate open source license. 

For more details, please visit: http://esim.fossee.in/circuit-simulation-project

Analysis of Short-Channel Effects in Junctionless DG MOSFETs #papers https://t.co/P2sqAueamw

Analysis of Short-Channel Effects in Junctionless DG MOSFETs #papers https://t.co/P2sqAueamw

— Wladek Grabinski (@wladek60) July 26, 2017

from Twitter https://twitter.com/wladek60

July 26, 2017 at 11:39AM
via IFTTT

[paper] A Compact Model for the Statistics of the Low-Frequency Noise of MOSFETs With Laterally Uniform Doping

M. Banaszeski da Silva, H. P. Tuinhout, A. Zegers-van Duijnhoven, G. I. Wirth and A. J. Scholten

"A Compact Model for the Statistics of the Low-Frequency Noise of MOSFETs With Laterally Uniform Doping" 

in IEEE TED, vol. 64, no. 8, pp. 3331-3336, Aug. 2017.
doi: 10.1109/TED.2017.2713301

Abstract: In this paper, we develop a compact physics-based statistical model for random telegraph noise-related low-frequency noise in bulk MOSFETS with laterally uniform doping. The proposed model is suited for modern compact device models, such as PSP, BSIM, and EKV. With our proposed model, one can calculate the expected value and the variability of the noise as a function of bias and device parameters. We validate the model through numerous experimental results from different CMOS nodes, down to 40 nm [read more...]

[paper] Compact On-Wafer Test Structures for Device RF Characterization

B. Kazemi Esfeh, K. Ben Ali and J. P. Raskin IEEE Fellow

Compact On-Wafer Test Structures for Device RF Characterization

in IEEE TED, vol. 64, no. 8, pp. 3101-3107, Aug. 2017
doi: 10.1109/TED.2017.2717196

Abstract: The main objective of this paper is to validate the radio frequency (RF) characterization procedure based on compact test structures compatible with 50um pitch RF probes. It is shown that by using these new test structures, the layout geometry and hence the on-chip space consumption for complete sets of passive and active devices, e.g., coplanar waveguide transmission lines and RF MOSFETs, is divided by a factor of two. The validity domain of these new compact test structures is demonstrated by comparing their measurement results with classical test structures compatible with 100–150um pitch RF probes. 50um -pitch de-embedding structures have been implemented on 0.18um RF silicon-on-insulator (SOI) technology. Cutoff frequencies and parasitic elements of the RF SOI transistors are extracted and the RF performance of trap-rich SOI substrates is analyzed under small- and large-signal conditions [read more...]

[mos-ak] [2nd Announcement and Call for Papers] 15th MOS-AK ESSDERC/ESSCIRC Workshop

MOS-AK ESSDERC/ESSCIRC Workshop
http://www.mos-ak.org/leuven_2017/
September 11, 2017 Leuven
2nd Announcement and Call for Papers

Together with the ASCENT Network represented by Profs Jim Greer and Nicolas Cordero as well as  International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) and all the Extended MOS-AK TPC Committee, we have pleasure to invite to the 15th MOS-AK Compact Modeling Workshop which will be organized for consecutive 15time as in integral part of the ESSDERC/ESSCIRC Conference in Leuven on Sept.11, 2017.

Planned MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors.

Important Dates:

• Preannouncement - March 2017
• Call for Papers - June 2017
• Final Workshop Program - August 2017
• MOS-AK Workshop - Sept.11, 2017

Venue: Leuven (B) <http://www.esscirc-essderc2017.org/venue>

Topics to be covered include the following among other related to the compact/SPICE modeling :

• Compact Modeling (CM) of the electron devices
• Advances in semiconductor technologies and processing
• Verilog-A language for CM standardization
• New CM techniques and extraction software
• Open Source TCAD/EDA modeling and simulation
• CM of passive, active, sensors and actuators
• Emerging Devices, TFT, CMOS and SOI-based memory cells
• Microwave, RF device modeling, high voltage device modeling
• Nanoscale CMOS devices and circuits
• Technology R&D, DFY, DFT and reliability/ageing IC Designs
• Foundry/Fabless Interface Strategies

Speakers: (tentative list in alphabetic order)

• Nicolas Cordero, Tyndal (IRL)
• Denis Flandre, CUL (B)
• Jim Greer, Tyndal (IRL)
• Benjamin Iniguez URV (SP)
• Marcelo Pavanello, FEI (BR)
• Jean-Pierre Raskin, CUL (B)
• Wim Schoenmaker, Magwel (B)
• Chika Tanaka, Toshiba (J)
• Ashkhen Yesayan, IRPhE (AM)

Prospective authors should submit abstract online

Manuscript submission deadline: 31sth July 2017 (Monday)
(any related inquiries can be sent to papers@mos-ak.org)

Online Workshop Registration

using online registration form <http://www.esscirc-essderc2017.org/howtoregister>
(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:

Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

WG080717

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[paper] A Compact Model for the Statistics of the Low-Frequency Noise of MOSFETs With Laterally Uniform Doping

A Compact Model for the Statistics of the Low-Frequency Noise of MOSFETs With Laterally Uniform Doping

M. Banaszeski da Silva; H. P. Tuinhout; A. Zegers-van Duijnhoven; G. I. Wirth; A. J. Scholten;

in IEEE Transactions on Electron Devices, vol.PP, no.99, pp.1-6
doi: 10.1109/TED.2017.2713301

Abstract: In this paper, we develop a compact physics-based statistical model for random telegraph noise-related low-frequency noise in bulk MOSFETS with laterally uniform doping. The proposed model is suited for modern compact device models, such as PSP, BSIM, and EKV. With our proposed model, one can calculate the expected value and the variability of the noise as a function of bias and device parameters. We validate the model through numerous experimental results from different CMOS nodes, down to 40 nm. [read more...]

Multiple Honors for E3S Theme Leader, Professor Tsu-Jae King Liu

(March 1, 2017) –   The Center for Energy Efficient Electronics Science is proud to announce Prof. Tsu-Jae King Liu has been named a newly elected member of the National Academy of Engineering. Prof. King Liu, who leads the E³S Nanomechanics theme was elected this year as one of only three members from UC Berkeley to this highest professional honor to an engineer. Last year in August, Prof. King Liu has also been chosen to serve on the Board of Directors at Intel Corporation. She was welcomed by Intel Chairman Andy Bryant: “[Prof. King Liu] brings a wealth of expertise in silicon technology and innovation that will be valuable for Intel in many areas as we navigate a significant business transition while continuing to lead in advancing Moore’s Law and harnessing its economic value.”In addition to this distinguished honor by Intel, last year the Semiconductor Research Corporation (SRC) announced Prof. King Liu has been selected to receive the 2016 SRC Aristotle Award. This esteemed award was created by the SRC Board of Directors in March 1995 with the intent "to acknowledge outstanding teaching in its broadest sense, emphasizing student advising and teaching." Heartiest congratulations from the entire E³S community to Prof. King Liu for these prestigious honors!

[paper] Design Strategies for Ultralow Power 10nm FinFETs

Design Strategies for Ultralow Power 10nm FinFETs

Abhijeet Walkea^a, Garrett Schlenvogtb^b, Santosh Kurineca^a

^aDepartment of Electrical & Microelectronic Engineering, RIT, New York, USA

^bTCAD Application Engineer, Silvaco

Received 12 June 2017, Accepted 19 June 2017, Available online 20 June 2017

Abstract: In this work, new design strategies for 10nm node NMOS bulk FinFET transistors are investigated to meet low power (LP) (20pA/μm< I_OFF <50pA/μm) and ultralow power (ULP) (I_OFF <20pA/μm) requirements using three dimensional (3D) TCAD simulations. The punch-through stop implant, source and drain junction placement and gate workfunction are varied in order to study the impact on the OFF-state current (I_OFF), transconductance (g_m), gate capacitance (C_gg) and intrinsic frequency (f_T). It is shown that the gate length of 20nm for the 10nm node FinFET can meet the requirements of LP transistors and ULP transistors by source-drain extension engineering, punch-through stop doping concentration, and choice of gate workfunction.

[read more https://doi.org/10.1016/j.sse.2017.06.012]

Rising SOI tide lifts Soitec into profit

Soitec SA (Bernin, France), developer of the "smart cut" method of silicon-on-insulator (SOI) wafer production, has reported its first profit for many years and is preparing to invest in facilities in France and possibly Singapore to meet rising demand for SOI wafers...

https://shar.es/1BtAZy


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[C4P] IEDM 2017

2017 IEDM CALL FOR PAPERS

The Annual International Electron Devices Meeting will be held at the Hilton San Francisco Union Square San Francisco, CA December 2-6, 2017

Abstract Deadline (four page final paper): August 2nd, 2017

To provide faster dissemination of the conference’s cutting-edge results, the abstract submission deadline has been moved to August 2nd for submission of four-page, camera-ready abstracts. Accepted papers will be published as-is in the proceedings

A Call for Papers flyer is available here: IEDM 2017 Call For Papers.

Customized Call for Papers for each of the technical subcommittee areas are also available:

• Circuit and Device Interaction (CDI)
• Characterization, Reliability, and Yield (CRY)
• Compound Semiconductor and High Speed Devices (CHS)
• Memory Technology (MT)
• Modeling and Simulation (MS)
• Material and interface modeling 
• Compact models
• Kinetic Monte Carlo and Molecular Dynamics
• Reliability and variability modeling
• Technology benchmarking
  New or trending areas include:
• First principle based quantum transport
• Process simulation with atomistic methods
• Self heating, interconnect and packaging
• Nano Device Technology (NDT)
• Optoelectronics, Displays, and Imagers (ODI)
• Power Devices (PD)
• Process and Manufacturing Technology (PMT)
• Sensors, MEMS, and BioMEMS (SMB)

[paper] Well-Posed Device Models for Electrical Circuit Simulation

Well-Posed Device Models for Electrical CircuitSimulation
A Guide to Creating Robust Device Models
A. Gokcen Mahmutoglu, Tianshi Wang, Archit Gupta and Jaijeet Roychowdhury
March 25, 2017

Synopsis: This document provides guidelines for creating computational device models that work well in simulation. We build our discussion around the mathematical notion of “well-posedness”. We show that the requirements for a model to be well-posed stem from the internal working mechanisms of simulators. Therefore, our main aim is to provide insight into the numerical procedures used by simulators in order to help model developers avoid ill-posedness issues. We start our discussion with an example that shows how an ill-posed Verilog-A model can produce different simulation results in different simulators. We then provide a step-by-step simulation case study. In this case study, we illustrate the role of device models in simulations by examining the steps a simulator goes through, from taking a netlist as input to producing a simulation result as output. Finally, we distill our discussion in a functional definition of a well-posed model. As an extension to our theoretical discussion, we also provide practical guidelines that should be followed by Verilog-A models in order to avoid ill-posedness issues [read more...]

This document is published as a part of the Nano-Engineered Electronic Device Simulation (NEEDS) initiative. NEEDS is an NSF-funded initiative whose charter includes the development of tools and techniques for the production of high-quality device models¹:
NEEDS has a vision for a new era of electronics that couples the power of billion-transistor CMOS technology with the new capabilities of emerging nano-devices and a charter to create high-quality models and a complete development environment that enables a community of compact model developers.

NEEDS Team: Purdue, MIT, UC Berkeley, and Stanford.”

¹For more information about NEEDS please visit https://nanohub.org/groups/needs/.