[paper] Avalanche Multiplication in SiGe HBTs

Zhang, Huaiyuan, Guofu Niu, Andries J. Scholten, and Marnix B. Willemsen

"Avalanche Multiplication Factor Modeling and Extraction at High Currents in SiGe HBTs"

IEEE Transactions on Electron Devices (2025)

DOI: 10.1109/TED.2025.3558114

1. Auburn University, Auburn, AL, USA

2. NXP, Eindhoven, The Netherlands

Abstract: A new compact model and an extraction method for avalanche multiplication factor (M-1) at high currents are proposed. At a fixed collector–base (CB) voltage (VCB), M-1 first decreases with increasing emitter current (IE) and then increases at higher currents when the Kirk effect occurs. Different forced-IE M-1 extraction techniques are evaluated, including a new compact modeling-based M-1 extraction technique that accurately captures the Early effect, the Kirk effect, and self-heating. The model is implemented in a development version of MEXTRAM and demonstrated experimentally to model both the current and bias dependence of M-1 and base current (IB). 

FIG: Simplified dc equivalent circuit of a transistor under forced IE,VCB 

and  fT(IE) meas/sim up to 150 mA at VCB = 1, 2, and 3 V (b)

Acknowledgment: The authors wish to acknowledge the support of the Compact Model Coalition (CMC).

[paper] A Compact Model for the Statistics of the Low-Frequency Noise of MOSFETs With Laterally Uniform Doping

A Compact Model for the Statistics of the Low-Frequency Noise of MOSFETs With Laterally Uniform Doping

M. Banaszeski da Silva; H. P. Tuinhout; A. Zegers-van Duijnhoven; G. I. Wirth; A. J. Scholten;

in IEEE Transactions on Electron Devices, vol.PP, no.99, pp.1-6
doi: 10.1109/TED.2017.2713301

Abstract: In this paper, we develop a compact physics-based statistical model for random telegraph noise-related low-frequency noise in bulk MOSFETS with laterally uniform doping. The proposed model is suited for modern compact device models, such as PSP, BSIM, and EKV. With our proposed model, one can calculate the expected value and the variability of the noise as a function of bias and device parameters. We validate the model through numerous experimental results from different CMOS nodes, down to 40 nm. [read more...]