#India Has $100 Billion Opportunity Through Domestic #Manufacturing Of Tablets, Laptops [ICEA] https://t.co/YIekOOiFME #semi https://t.co/S0rb3I1jXA

#India Has $100 Billion Opportunity Through Domestic #Manufacturing Of Tablets, Laptops [ICEA] https://t.co/YIekOOiFME #semi pic.twitter.com/S0rb3I1jXA

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[paper] Compact Model for Power MOSFET

Abdelghafour Galadi

PSPICE compact model for power MOSFET based on manufacturer datasheet

DOI:10.1088/1757-899X/948/1/012007

National School of Applied Sciences of Safi, Cadi Ayyad University, Marrakech (MA)

Abstract: In this paper, large signal model for power MOSFET devices is presented. The proposed model includes quasi-saturation effect and describes accurately the electrical behavior of the power MOSFET devices. The large signal model elements will be provided based on the device structure. Furthermore, the model parameters are extracted from measurements considering the voltages depending effect of the nonlinear gate-source, gate-drain and drain-source interelectrode capacitances. Excellent agreements will be shown between the simulated and the datasheet data. Finally, a description of the model will be provided along with the parameter extraction procedure.

Fig: a) Conventional power MOSFET structure with b) its subcircuit elements. 

[paper] HEMT RF/Analog Performance

M. Khaouani¹,H. Bencherif², A. Hamdoune¹, A. Belarbi³, Z. Kourdi⁴

RF/analog Performance Assessment of High Frequency, Low Power In_0.3Al_0.7As/InAs/InSb/In_0.3Al_0.7As HEMT Under High Temperature Effect

Transactions on Electrical and Electronic Materials

The Korean Institute of Electrical and Electronic Material Engineers 2020

DOI: 10.1007/s42341-020-00250-8

1 Department of Genie Electric and Electronics, Unit Research of Material and Renewable Energies, University Aboubek Belkaid, Tlemcen, Algeria
2 LAAAS Laboratory, University of Batna 2, Batna, Algeria
3 Center Exploitation Telecommunication Satellite– Bouchaoui-Alger, Algeria Space Agency, Algiers, Algeria
4 Center Exploitation Telecommunication Satellite– Oran-Alger, Algeria Space Agency, Algiers, Algeria

In_0.3Al_0.7As/InAs/InSb/In_0.3Al_0.7As In this paper, we performed a Pseudo-morphic High Electron Mobility Transistors (pHEMT) In_0.3Al_0.7As/InAs/InSb/In_0.3Al_0.7As using commercial TCAD. RF and analog electrical characteristics are assessed under high temperature effect. The impact of the temperature is evaluated referring to a device at room temperature. In particular, the threshold voltage (Vth), transconductance (gm), and Ion/Ioff ratio are calculated in the temperature range of 300K to 700K. The primary device exhibits a drain current of 950mA, a Vth of -1.75V, a high value of gm of 650 mS/mm, Ion/Ioff ratio of 1E6, a transition frequency (fT) of 790GHz, and a maximum frequency (fmax) of 1.4THz. The achieved results show that increasing temperature act to decrease current, reduce gm, and Ion/Ioff ratio. In more detail high temperature causes a phonon scattering mechanism happening that determine in turn a reduced drain current and shift positively the threshold voltage resulting in hindering the device DC/AC capability. 

Fig: 2D cross section of In_0.3Al_0.7As/InAs/InSb/In_0.3Al_0.7AsAs PHEMT

[paper] Verilog-A Ion Sensitive FET for pH Sensor

Megha Agrawal, Nidhi Agrawal, Alpana Agarwal and Anil K. Saini*

Modeling of Ion Sensitive Field Effect Transistor for pH Sensor using Verilog-A

 Recent Advancement in Communication System & Image Processing

RACISP-2012 at: BKBIET, Pilani

Thapar University, PATIALA – 147004, Punjab

*Central Electronics Engineering Research Institute, PILANI – 333031, Rajasthan

Abstract: ISFET semiconductor technology enables the design of true solid state pH sensor. An ISFET can be modeled by considering it as two fully uncoupled stages: an electronic stage i.e., the MOSFET which is the starting structure of the ISFET and an Electro-chemical stage i.e., the electrolyte–insulator interface which is pH dependent. This paper describes the modeling of ISFET for pH measurement using Verilog A which is compatible with cadence environment. Any change in pH directly affects the threshold voltage of ISFET. To measure this change in pH, ISFET is configured in such a way so that change in threshold voltage can be directly detected. For this purpose a sensing read-out has been designed using Gate complementary ISFET/MOSFET pair (CIMP) technique. Simulated result shows good linearity between output voltage of sensing readout circuit with pH variation for the range of 1 to12. The ISFET is thermally instable due to semiconductor properties and pH dependency on temperature, which in turn affects the pH reading of the solution at a temperature other than room temperature with slope of +0.69mV/0C, +1.25mV/0C and +1.60mV/0C respectively for pH= 4, for pH=7 and for pH=10.

Fig: a) n-channel ISFET structure and b) its equivalent electric circuit [ref]

Acknowledgment: The work is financially supported by Department of Information Technology, Ministry of Communication & Information Technology, Government of India, under SMDP-VLSI (Phase II) project.

[ref] Sergio Martinoia, Giuseppe Massobrio, “A Behavioral Macromodel of the ISFET in SPICE,” Sensors and Actuators B, Vol. 62, pp. 182–189, 2000

Appendix A

// Verilog-A Code for ISFET [ref]
`include "constants.vams"
`include "disciplines.vams"
module ISFET(ref,gm,ph);
inout ref,gm,ph;
electrical ref,gm,ph;
real EPH;
real T;
electrical node;

electrical x,y;
// PARAMETERS FOR ISFET

parameter real NAv = 6.023E26; //Avogadros constant(1/MOLE)

// ISFET geometrical parameters

parameter real DIHP =0.1E-9;

parameter real DOHP =0.3E-9;

//ISFET electrochemical parameters

parameter real KA = 15.8;

parameter real KB = 63.1E-9;

parameter real KN = 1E-10;

parameter real Nsil = 3.0E+18;

parameter real Nnit = 2.0E+18;

parameter real Cbulk = 0.1;

parameter real epso = 8.85E-12;

parameter real epsihp = 32; //relative permittivity of the Inner Helmholtz layer

parameter real epsohp = 32; //relative permittivity of the Outer Helmholtz layer

parameter real epsw = 78.5; //relative permittivity of the bulk electrolyte solution

//Reference-electrode electrochemical parameters

parameter real Eabs = 4.7; //absolute potential of the standard hydrogen electrode

parameter real Erel = 0.2;

parameter real Phim = 4.7; //work function of the metal back contact

parameter real Philj = 1E-3; //liquid-junction potential difference between the ref

solution and the electrolyte

parameter real Chieo = 3E-3; //surface dipole potential

real ET; //THERMAL COFFICIENT
real sq;
real CH, CD, CEQ, CB;
real Eref;

analog begin

T= $temperature;

ET= (`P_Q /(`P_K * T));

sq = sqrt(8*`P_EPS0*epsw*`P_K * T);

CB = (NAv*Cbulk);

CH = ((`P_EPS0*epsihp*epsohp) / (epsohp*DIHP + epsihp*DOHP));

CD = (sq*ET*0.5)*sqrt(CB);

CEQ = 1/(1/CD + 1/CH);

V(ref,node) <+ Eabs - Phim - Erel + Chieo + Philj;

Eref = V(ref,node);

V(x)<+ log(KA*KB)+4.6*V(ph);

V(y)<+ log(KA)+2.3*V(ph);

V(gm,node) <+ (`P_Q / CEQ) * (Nsil * ((limexp(-2 * V(gm,node) * ET)– limexp

(V(x))) / (limexp(-2 * V(gm,node) * ET) + limexp(V(y)) * limexp(-1 * V

(gm,node)*ET) + limexp(V(x)))) + Nnit*((limexp(-1 * V(gm,node)*ET))/(limexp(-1* V(gm,node)*ET)

+ (KN/KA) * limexp(V(y)))));

end

capacitor #(.c(CEQ)) Cq(node,gm);

resistor #(.r(1G)) RP1(x,gnd);

resistor #(.r(1G)) RP2(y,gnd);

resistor #(.r(1k)) RPH(ph,gnd);

endmodule

[paper] Editorial Special Section on ESSDERC

IEEE TED, Vol. 67, No. 11, November 2020

Mid-September 2020, we were supposed to celebrate in Grenoble the 50th anniversary of the European SolidState Device Research Conference and European Solid-State Circuits Conference (ESSDERC-ESSCIRC), which is the most important European conference dedicated to solid-state devices and circuits. However, in April 2020, more than one-third of the global population was under severe lock-down as a result of the protective public health measures imposed by the different governments, states, or provinces. Because of the COVID-19 pandemic, the ESSDERC-ESSCIRC organizing and steering committees, together with the sponsoring SSCS and EDS IEEE societies, decided to reschedule the in-person conference to September 6–9, 2021, in Grenoble, to add new virtual “Educational Events” held on September 14 and 15, 2020 (presentations available till October 16, 2020, at https://www.esscirc-essderc2020.org/) as well as to invite the ESSDERC-ESSCIRC research community to submit publications to the IEEE TRANSACTIONS ON ELECTRON DEVICES (TED) and to the IEEE SOLID-STATE CIRCUITS LETTERS (SSC-L), respectively, in a brief format. All of these initiatives met great success. Especially, more than 47 TED submissions were received and reviewed, and 32 papers were accepted and have been included in this dedicated section of the November TED issue.

We would like to thank all the authors for taking this opportunity to keep the ESSDERC-ESSCIRC momentum, all the IEEE reviewers for their reactivity, and all the ESSDERC-ESSCIRC sponsors for their trust in this difficult time. Let us think with a positive mind, and acknowledge that this experience opens a new and fruitful collaboration between ESSDERC and TED.

We hope you will enjoy reading these high-quality papers. Stay safe

FRANCOIS ANDRIEU, TPC Chair
CEA-Leti
Université Grenoble Alpes
38054 Grenoble, France

GIOVANNI GHIONE, Editor-in-Chief
Dipartimento di Elettronica e Telecomunicazioni
Politecnico di Torino
10129 Torino, Italy

Editorial Special Section on ESSDERC

 IEEE TED, Vol. 67, No. 11, November 2020

1. Generalized Constant Current Method for Determining MOSFET Threshold Voltage M. Bucher, N. Makris, and L. Chevas pp.4559
2. Performance and Low-Frequency Noise of 22-nm FDSOI Down to 4.2 K for Cryogenic Applications (Invited Paper) B. Cardoso Paz, M. Cassé, C. Theodorou, G. Ghibaudo, T. Kammler, L. Pirro, M. Vinet, S. de Franceschi, T. Meunier, and F. Gaillard pp.4563
3. A Method for Series-Resistance-Immune Extraction of Low-Frequency Noise Parameters in Nanoscale MOSFETs A. Tataridou, G. Ghibaudo, and C. Theodorou pp.4568
4. Analytical Model for Interface Traps-Dependent Back Bias Capability and Variability in Ultrathin Body and Box FDSOI MOSFETs W. Chen, L. Cai, X. Liu, and G. Du pp.4573
5. Polarization Independent Band Gaps in CMOS Back-End-of-Line for Monolithic High-Q MEMS Resonator Confinement R. Hudeczek and P. Baumgartner pp.4578
6. Out-of-Equilibrium Body Potential Measurement on Silicon-on-Insulator With Deposited Metal Contacts M. Alepidis, A. Bouchard, C. Delacour, M. Bawedin, and I. Ionica pp.4582
7. Evaluation of High-Temperature High-Frequency GaN-Based LC-Oscillator Components A. Ottaviani, P. Palacios, T. Zweipfennig, M. Alomari, C. Beckmann, D. Bierbüsse, J. Wieben, J. Ehrler, H. Kalisch, R. Negra, A. Vescan, and J. N. Burghartz pp.4587
8. Analysis of Gate-Metal Resistance in CMOS-Compatible RF GaN HEMTs R. Y. ElKashlan, R. Rodriguez, S. Yadav, A. Khaled, U. Peralagu, A. Alian, N. Waldron, M. Zhao, P. Wambacq, B. Parvais, and N. Collaert pp.4592
9. Characterization and TCAD Modeling of Mixed-Mode Stress Induced by Impact Ionization in Scaled SiGe HBTs N. Zagni, F. M. Puglisi, G. Verzellesi, and P. Pavan pp.4597
10. Hot-Electron Effects in AlGaN/GaN HEMTs Under Semi-ON DC Stress A. Minetto, B. Deutschmann, N. Modolo, A. Nardo, M. Meneghini, E. Zanoni, L. Sayadi, G. Prechtl, S. Sicre, and O. Häberlen pp.4602
11. Vertically Replaceable Memory Block Architecture for Stacked DRAM Systems by Wafer-on-Wafer (WOW) Technology S. Sugatani, N. Chujo, K. Sakui, H. Ryoson, T. Nakamura, and T. Ohba pp.4606
12. Reliability of Logic-in-Memory Circuits in Resistive Memory Arrays T. Zanotti, C. Zambelli, F. M. Puglisi, V. Milo, E. Pérez, M. K. Mahadevaiah, O. G. Ossorio, C. Wenger, P. Pavan, P. Olivo, and D. Ielmini pp.4611
13. IGZO-Based Compute Cell for Analog In-Memory Computing—DTCO Analysis to Enable Ultralow-Power AI at Edge D. Saito, J. Doevenspeck, S. Cosemans, H. Oh, M. Perumkunnil, I. A. Papistas, A. Belmonte, N. Rassoul, R. Delhougne, G. Kar, P. Debacker, A. Mallik, D. Verkest, and M. H. Na pp.4616
14. Array-Level Programming of 3-Bit per Cell Resistive Memory and Its Application for Deep Neural Network Inference Y. Luo, X. Han, Z. Ye, H. Barnaby, J.-s. Seo, and S. Yu pp.4621
15. Ultrahigh-Density 3-D Vertical RRAM With Stacked Junctionless Nanowires for In-Memory-Computing Applications M. Ezzadeen, D. Bosch, B. Giraud, S. Barraud, J.-P. Noël, D. Lattard, J. Lacord, J. M. Portal, and F. Andrieu pp.4626
16. Thermal Stress-Aware CMOS–SRAM Partitioning in Sequential 3-D Technology S. M. Salahuddin, E. Dentoni Litta, A. Gupta, R. Ritzenthaler, M. Schaekers, J.-L. Everaert, H. Yu, A. Vandooren, J. Ryckaert, M.-H. Na, and A. Spessot pp.4631
17. Cryogenic Operation of Thin-Film FDSOI nMOS Transistors: The Effect of Back Bias on Drain Current and Transconductance M. Cassé, B. Cardoso Paz, G. Ghibaudo, T. Poiroux, S. Barraud, M. Vinet, S. de Franceschi, T. Meunier, and F. Gaillard pp.4636
18. Enhanced Ultraviolet Avalanche Photodiode With 640-nm-Thin Silicon Body Based on SOI Technology I. Sabri Alirezaei, N. Andre, and D. Flandre pp.4641
19. TCAD Study of VLD Termination in Large-Area Power Devices Featuring a DLC Passivation L. Balestra, S. Reggiani, A. Gnudi, E. Gnani, J. Dobrzynska, and J. Vobecký pp.4645
20. Analysis of MIS-HEMT Device Edge Behavior for GaN Technology Using New Differential Method R. Kom Kammeugne, C. Leroux, J. Cluzel, L. Vauche, C. Le Royer, R. Gwoziecki, J. Biscarrat, F. Gaillard, M. Charles, E. Bano, and G. Ghibaudo pp.4649
21. Influence of Substrate Resistivity on Porous Silicon Small-Signal RF Properties G. Godet, E. Augendre, J. Lugo-Alvarez, H. Jacquinot, F. X. Gaillard, T. Lorne, E. Rolland, T. Taris, and F. Servant pp.4654
22. Free Carrier Mobility, Series Resistance, and Threshold Voltage Extraction in Junction FETs N. Makris, M. Bucher, L. Chevas, F. Jazaeri, and J.-M. Sallese pp.4658
23. Local Variability Evaluation on Effective Channel Length Extracted With Shift-and-Ratio Method J. P. Martinez Brito and S. Bampi pp.4662
24. Charge-Based Model for the Drain-Current Variability in Organic Thin-Film Transistors Due to Carrier-Number and Correlated-Mobility Fluctuation A. Nikolaou, G. Darbandy, J. Leise, J. Pruefer, J. W. Borchert, M. Geiger, H. Klauk, B. Iniguez, and A. Kloes pp.4667
25. Macromodel for AC and Transient Simulations of Organic Thin-Film Transistor Circuits Including Nonquasistatic Effects J. Leise, J. Pruefer, A. Nikolaou, G. Darbandy, H. Klauk, B. Iniguez, and A. Kloes pp.4672
26. Compact Modeling and Behavioral Simulation of an Optomechanical Sensor in Verilog-A H. Elmi Dawale, L. Sibeud, S. Regord, G. Jourdan, S. Hentz, and F. Badets pp.4677
27. TCAD Simulation Framework of Gas Desorption in CNT FET NO2 Sensors S. Carapezzi, S. Reggiani, E. Gnani, and A. Gnudi pp.4682
28. Conductance in a Nanoribbon of Topologically Insulating MoS2 in the 1T Phase V. Sverdlov, A.-M. B. El-Sayed, H. Kosina, and S. Selberherr pp.4687
29. Vt Extraction Methodologies Influence Process Induced Vt Variability: Does This Fact Still Hold for Advanced Technology Nodes? M. S. Bhoir, T. Chiarella, J. Mitard, N. Horiguchi, and N. R. Mohapatra pp.4691
30. Multidomain Negative Capacitance Effect in P(VDF-TrFE) Ferroelectric Capacitor and Passive Voltage Amplification K. J. Singh, A. Bulusu, and S. Dasgupta pp.4696
31. Monte Carlo Comparison of n-Type and p-Type Nanosheets With FinFETs: Effect of the Number of Sheets F. M. Bufler, D. Jang, G. Hellings, G. Eneman, P. Matagne, A. Spessot, and M. H. Na pp.4701
32. Impact of Width Scaling and Parasitic Series Resistance on the Performance of Silicene Nanoribbon MOSFETs M. Poljak pp.4705

[book] Emerging Trends in Terahertz Solid-State Physics and Devices by Springer Nature https://t.co/d6ic3XhucH. https://t.co/gaEUA16nMZ #semi https://t.co/N1Gve7JdIy

[book] Emerging Trends in Terahertz Solid-State Physics and Devices by Springer Nature https://t.co/d6ic3XhucH. https://t.co/gaEUA16nMZ #semi pic.twitter.com/N1Gve7JdIy

— Wladek Grabinski (@wladek60) November 17, 2020

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Fwd: Webinar on Material Growth, Characterization of Semiconductors and Device Applications Through Atomistic TNL TCAD

We, Tech Next Lab jointly with IEEE are organizing online Webinar on Material Growth, Characterization of Semiconductors and Device Applications Through Atomistic TNL TCAD. You may register on below given link and forward webinar link to other participants who are interested:

 

Date: Saturday, 21st November 2020 Time: 17.00 to 18.00 PM

 

Venue: Webinar, https://ieeemeetings.webex.com/mw3300/mywebex/default.do?nomenu=true&siteurl=ieeemeetings&service=6&rnd=0.4120147922217301&main_url=https%3A%2F%2Fieeemeetings.webex.com%2Fec3300%2Feventcenter%2Fevent%2FeventAction.do%3FtheAction%3Dlandingfrommail%26%26%26EMK%3D4832534b00000004dd1533ca73887031a5f6aba9a5ddeab7c1c28a4b4eefc99e1854c972162366b3%26siteurl%3Dieeemeetings%26confViewID%3D177688211646058031%26SourceId%3Db3a103b9683d3bb4e053a1a2f00adaf9%26encryptTicket%3DSDJTSwAAAASCf8FNVc5sRaYU7OZ07E9Pk4H0zwaXZ4GvrYGL05ZPnw2%26email%3Darif.sohel%2540mjcollege.ac.in

 

 

We are pleased to introduce unmatched family of Innovative Atomistic TNL TCAD simulators, including EpiGrow, FullBand, HallMobility and Monte Carlo Particle Device simulators. All products are proprietary products of Tech Next Lab (P) Ltd. We provide instant technical and sales solution for the queries and feedback come from the customers. You may find more details about TNL TCAD tools on our website: www.technextlab.com You may download TNL TCAD from our website and ask us for evaluation license. Feel Free to write us your technical and sales related queries, we will revert to you with in next working day.

 

Looking forward to meeting you.

Best Regards,

 

 TNL Framework: TNL Framework includes family of innovative simulators based on atomistic level. It provides innovative technology solution to semiconductor industry. The technology development is expensive process and suffers with lot of technical challenges & issues. TNL framework is designed to innovate the semiconductor device designing. It accomodate atomistic based thin film growth simulator, full band simulator, material characterization simulator and Monte Carlo particle device simulator. 

 EpiGrow Simulator: EpiGrow simulator is world's first commercial innovative atomistic epitaxial growth simulator to grow thin film inside MBE/MOCVD reactors. EpiGrow simulator is powerful tool to trace atomistic thin and thick film growth inside reactors. Kinetic Monte Carlo algorithms keeps Randomness in adsorption, hopping & desorption processes. It offer cost economical solution for thin film growth technology even for nm thin monolayer. Capable to predict the initial conditions for Molecular Beam Epitaxy & Molecular Organic Chemical Vapor Deposition (MOCVD) reactors. Capable to calculate the lattice constant of monolayer, trace different types of defects, and strain. Optimizer provides flexibility to optimize initial conditions with EpiGrow Simulator and run design of experiments over the computer.

 FullBand Simulator:   Full Band Simulator is powerful tool, extends the empirical pseudopotential method to include semiconductors with the zincblende as well as wurtzite structures and simulates electronic band structures with appropriate pseudopotential form factors chosen from the reported reputed references for binary alloy semiconductor materials and interpolate the pseudopotential form factors for ternary alloy semiconductor materials to simulate the full electronic band structures of ternary materials. The bowing of band energies and their deformation potentials is included inside simulator in form of alloy disorder. Capable to simulate the full electronic band structures for the lattice constant of monolayer provided by users. Different types of physical parameters e.g. carrier velocity, effective mass and density of states can be easily tracable on the full electronic band structures of the chosen materials. Provides flexibility to users to chose lattice constant and analyse the full electronic band structures over computer.

 Hall Mobility Simulator: Hall Mobility Simulator is powerful tool, simulates carriers transport on full energy band. The microscopic simulation of the motion of individual particles in the presence of the forces acting on them due to external fields as well as the internal fields of the crystal lattice and other charges in the system. In solids, such as semiconductors and metals, transport is known to be dominated by random scattering events due to impurities, lattice vibrations, etc. has been inputted through Monte Carlo technique, which randomize the momentum and energy of charge particles in time. Hence, stochastic techniques to model these random scattering events are particularly useful in describing transport in semiconductors, in particular the Monte Carlo method. Provides flexibility to users to initialize the carriers over full energy band and analyze the transport of carrier to simulate the ensemble velocity of carriers under external electromagnetic forces on computer.

 MC Particle Device Simulator: World's Fastest Monte Carlo Particle Device simulator includes transport model solution with a self -consistent Boltzmann-Poisson equation and a GUI based feature helps users to select device geometry and doping density in 2D and 3D. The different carrier scattering mechanisms has major influence on the performance of device output and dependent on the density of states (DOS) in each valley which can be accurately inputted through full band structure. The effect of equilibrium states of carrier before start of free flight of carrier has been incorporated in term of inclusion of depletion region through movement of the ensemble of carriers under influence of external electrostatic field obtained by solving the Poisson equation. The quantum confinement effect includes density gradient approach and effective potential approach for computation of quantum confinement effects on the carrier transport under influence of external forces. Particle Device Simulator (PDS) is exploited for unipolar as well as bipolar semiconductor technologies based devices including MOSFET, Multigate FETS, HEMT and P-N junction devices.

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What Is a Graphene Field Effect Transistor (#GFET)?

What Is a Graphene Field Effect Transistor (#GFET)? Construction, Benefits, and Challenges - Technical Articles https://t.co/lTzuC59m5j #semi 

 

— Wladek Grabinski (@wladek60) November 16, 2020

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Digi-Key releases 1.5 million SnapEDA #CAD #models https://t.co/IzCT3WnWTC #semi https://t.co/BBXV146WQ7

Digi-Key releases 1.5 million SnapEDA #CAD #models https://t.co/IzCT3WnWTC #semi pic.twitter.com/BBXV146WQ7

— Wladek Grabinski (@wladek60) November 13, 2020

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RT @gvanrossum: I decided that retirement was boring and have joined the Developer Division at Microsoft. To do what? Too many options to say! But it’ll make using Python better for sure (and not just on Windows :-). There’s lots of open source here. Watch this space. . #semi https://t.co/kJI0LT4jUA

RT @gvanrossum: I decided that retirement was boring and have joined the Developer Division at Microsoft. To do what? Too many options to say! But it’ll make using Python better for sure (and not just on Windows :-). There’s lots of open source here. Watch this space.
.#semi https://t.co/kJI0LT4jUA

— Wladek Grabinski (@wladek60) November 13, 2020

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November 13, 2020 at 07:35PM
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Fwd: Elena Gnani DL - Tunnel FETs: Device Physics and Realizations

To view complete details for this event, click here to view the announcement

Elena Gnani DL - Tunnel FETs: Device Physics and Realizations

---

The EDS Germany Chapter and NanoP proudly presents Elena Gnani from University of Bologna, Bologna, Italy for a Distinguished Lecture on "Tunnel FETs: Device Physics and Realizations". The lecture will be held on 18th January 2021 at 3pm Berlin time.

Date and Time

• Date: 18 Jan 2021
• Time: 03:00 PM to 04:00 PM
• All times are Europe/Berlin
• Add Event to Calendar
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Location

The Distiguished Lecture will be held via Zoom. Login information provided before the event and requires registration.

Hosts

• Germany Section Chapter, ED15
• Co-sponsored by NanoP, Technische Hochschule Mittelhessen - University of Applied Sciences

Registration

• Starts 12 November 2020 04:30 PM
• Ends 16 January 2021 05:00 PM
• All times are Europe/Berlin
• No Admission Charge

• Register Now

[mos-ak] [2nd Announcement and C4P] 13th Virtual MOS-AK Workshop, Silicon Valley, Dec. 10-11 2020

Together with  local organization team, International MOS-AK Board of R&D Advisers as well as all the Extended MOS-AK TPC Committee, we have the pleasure to invite to consecutive, 13th International MOS-AK Workshop which will be organized as the virtual/online event on Dec. 10-11, 2020 (preceding the IEDM and Q4 CMC Meetings)

Planned virtual 13th International MOS-AK Workshop aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring academic and industrial experts in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Venue: Virtual/Online

Online Workshop Registration to be open 

(any related enquiries can be sent to registration@mos-ak.org)

Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:

• Compact Modeling (CM) of the electron devices
• Advances in semiconductor technologies and processing
• Verilog-A language for CM standardization
• New CM techniques and extraction software
• Open Source (FOSS) TCAD/EDA modeling and simulation
• CM of passive, active, sensors and actuators
• Emerging Devices, TFT, CMOS and SOI-based memory cells
• Microwave, RF device modeling, high voltage device modeling
• Nanoscale CMOS, BiCMOS, SiGe, GaN, InP devices and circuits
• Technology R&D, DFY, DFT and reliability/ageing IC designs
• Foundry/Fabless Interface Strategies

Important Dates: 

• 2nd Announcement: Nov. 2020
  
• Final Workshop Program: Dec. 2020
  
• Virtual MOS-AK Workshop: Dec. 10-11, 2020
  

Online Abstract Submission to be open 

(any related enquiries can be sent to abstbstracts@mos-ak.org)

Extended MOS-AK Committee

WG10112020

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[mos-ak] [online publications] Virtual MOS-AK Workshops (Sept. 2020)

Arbeitskreis Modellierung von Systemen und Parameterextraktion 

Modeling of Systems and Parameter Extraction Working Group

Virtual MOS-AK Workshops (Sept. 2020)

Local organization teams together with the International MOS-AK Board of R&D Advisers as well as all the Extended MOS-AK TPC Committee have organized two subsequent virtual/online workshops

• MOS-AK Workshop as ESSDERC/ESSCIRC Virtual Educational Event
  • http://www.mos-ak.org/grenoble_2020/
  • Sept.15, 2020 (16:00 - 17:00 CET with livestreaming) 
• MOS-AK Workshop at THM Giessen (D),
  • http://www.mos-ak.org/giessen_2020/
  • Tue 29.09.2020 - MOS-AK
  • Wed 30.09.2020 - MOS-AK & IEEE EDS MQ
  • Thu 01.10.2020 - IEEE EDS MQ & SB MOS Symposium

Online Publications:

There are MOS-AK technical presentations covering selected aspects of the compact/SPICE modeling and its Verilog-A standardization (see  the slide presentations online at respective corresponding links).

Postworkshop Publications:

Selected best MOS-AK technical presentation will be recommended for further publication in a special Solid State Electronics issue on compact modeling planned for 2021

The MOS-AK Association plans to continue its standardization efforts by organizing future compact modeling meetings, workshops and courses around the globe thru 2020 and next 2021 year, including:

• Virtual MOS-AK Silicon Valley (US), Dec. 10-11 2020 
• FOSDEM CAD/EDA DevRoom, ULB, (B) Feb. 2021
• MOS-AK at LAEDC (MX),  April 18-20 2021
• FOSS TCAD/EDA at 5NANO2021, Kottayam (IN) April 2021
• MIXDES CM Session, Wroclaw (PL), June 2021
  with IEEE EDS MQ
• 5th Sino MOS-AK Xi'an (CN), July  2021
• 19th MOS-AK at ESSDERC/ESSCIRC, Grenoble (F) Sept. 2021
• 14th US MOS-AK Workshop, Silicon Valley (US) Dec. 2021
  in timeframe of IEDM and Q4 CMC Meetings

W.Grabinski on the behalf of International MOS-AK Committee  

WG10112020

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Software Freedom in Europe

"Software Freedom in Europe" is the yearly report of the Free Software Foundation Europe e.V. (#FSFE). In one document, it gives you a breakdown of important things and achieved during the last 12 monthshttps://t.co/mW0fWgiLLP #semi pic.twitter.com/TN2C1uQzgI

— Wladek Grabinski (@wladek60) November 10, 2020

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November 10, 2020 at 02:29PM
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Open-Source Software Moves into Industry 4.0 #IOT #robotics #sensors #semi https://t.co/sYQCsz9uQo https://t.co/yB17jmBu0t

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— Wladek Grabinski (@wladek60) November 9, 2020

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November 09, 2020 at 11:53AM
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The Status Of #Semi #Manufacturing In #India. This leads to the question, what are the missing links? https://t.co/7kd7won4WD https://t.co/sh3NMQk8zY

The Status Of #Semi #Manufacturing In #India. This leads to the question, what are the missing links? https://t.co/7kd7won4WD pic.twitter.com/sh3NMQk8zY

— Wladek Grabinski (@wladek60) November 9, 2020

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November 09, 2020 at 09:34AM
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Create #Free #Silicon #Chips Courtesy of Google, SkyWater, and Efabless! https://t.co/bSvD2y7NeP #semi https://t.co/YdP54UY2q3

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— Wladek Grabinski (@wladek60) November 6, 2020

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November 06, 2020 at 01:42PM
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[paper] TFT for Mixed Signal and Analog Computation

Eva Bestelink, Olivier de Sagazan, Lea Motte, Max Bateson, Benedikt Schultes, S. Ravi P. Silva,

and Radu A. Sporea

Versatile Thin‐Film Transistor with Independent Control of Charge Injection and Transport

for Mixed Signal and Analog Computation

Adv. Intell. Syst.. (2020) pp.1-9, DOI:10.1002/aisy.202000199 

Abstract: New materials and optimized fabrication techniques have led to steady evolution in large area electronics, yet significant advances come only with new approaches to fundamental device design. The multimodal thin-film transistor introduced here offers broad functionality resulting from separate control of charge injection and transport, essentially using distinct regions of the active material layer for two complementary device functions, and is material agnostic. The initial implementation uses mature processes to focus on the device’s fundamental benefits. A tenfold increase in switching speed, linear input–output dependence, and tolerance to process variations enable low-distortion amplifiers and signal converters with reduced complexity. Floating gate designs eliminate deleterious drain voltage coupling for superior analog memory or computing. This versatile device introduces major new opportunities for thin-film technologies, including compact circuits for integrated processing at the edge and energy-efficient analog computation.

Figure: Outcomes of separating control for injection and conduction shown via TCAD simulation. a) MMT transient response is much faster than conventional contact-controlled TFTs

b) A MMT with multiple, appropriately sized CG1 gates can function as a digital-to-analog converter (DAC) with CG2 providing an enabling, sampleand-hold (S/H) function. 

Acknowledgements: E.B. and R.A.S. contributed equally to this work. This work was partly supported through EPSRC grants EP/R511791/1 and EP/R028559/1 and Research Fellowship 10216/110 from the Royal Academy of Engineering of Great Britain. Device fabrication had been performed on the NanoRennes platform. The authors thank Dr. Brice Le Borgne for initial liaison and process discussions, Prof. John M. Shannon for on-going advisory meetings, Prof. Craig Underwood for reviewing the manuscript, Dr. David Cox and Mr. Mateus Gallucci Masteghin for assistance with the SEM images.

IEEE Germany EDS Chapter Elections

The IEEE Germany EDS Chapter has elected new ExCom members for the term 2020/2021. An exciting new leadership team has been built to establish EDS activities in Germany.

The new ExCom:

• Chair: Mike Schwarz (TH Mittelhessen)
• Vice Chair: Joachim Burghartz (Universität Stuttgart, IMS Chips)
• Treasurer: Manfred Berroth (Universität Stuttgart)
• Secretary: Sevda Abadpour (Karlsruhe Institute of Technology)

Further information is available online https://r8.ieee.org/germany-eds

[paper] Local Variability Evaluation on Effective Channel Length

Juan Pablo Martinez Brito, Graduate Student Member, IEEE, 

and Sergio Bampi, Senior Member, IEEE

Local Variability Evaluation on Effective Channel Length

Extracted with Shift-and-Ratio Method

IEEE TED, vol. 67, no. 11, pp. 4662-4666, Nov. 2020

doi: 10.1109/TED.2020.3017178

Abstract: In this study, the local variation of the effective channel reduction parameter (ΔL=Lm−Leff) of a MOSFET is extracted by means of the traditional shift-and-ratio (SAR) method. ΔL is then correlated with the threshold voltage difference (ΔVTH) between the device under test (DUT) and the reference device. It is demonstrated that there exists an optimal VG range for extracting reliable values of L through the SAR method. Statistical data analysis shows that for R≈ (Llong/Lshort)≈25, better results are achieved since the value of σ(ΔL) varies typically as the reciprocal 1/√ W. The test structure used in this work is a Kelvin-based 2-D addressable MOSFET matrix implemented in 180-nm bulk CMOS technology. The sample space is of 2304 devices divided into nine subgroups of 256 same size closely placed nMOSFETs.

Fig: (a) Full circuit micrograph (b) MOSFET Matrix structure (c) Zoomed-in view at DUTs 

Acknowledgment: The authors would like to thank and acknowledge the Brazilian public company CEITEC S.A. Semiconductors for the measurement infrastructure, the CAD Support Center (NSCAD) at Federal University of Rio Grande do Sul (UFRGS) for electronic design automation (EDA) support, and Silterra Inc. for the silicon prototyping services.

ASCENT project

Applications and Systems-driven Center for Energy-Efficient integrated Nano Technologies

The Mission of the ASCENT Center is to transcend the current limitations of high-performance transistors confined to a single planar layer of integrated circuit by pioneering vertical monolithic integration of multiple interleaved layers of logic and memory, by demonstrating beyond-CMOS device concepts that combine processing and memory functions, heterogeneously integrating functionally diverse nano-components into integrated microsystems and by demonstrating in-memory compute kernels to accelerate future data-intensive at-scale cognitive workloads.

Researchers at ASCENT pursue four areas of technology including three-dimensional integration of device technologies beyond a single planar layer (vertical CMOS); spin-based device concepts that combine processing and memory functions (beyond CMOS); heterogeneous integration of functionally diverse nano-components into integrated microsystems (heterogeneous integration fabric); and hardware accelerators for data intensive cognitive workloads (merged logic-memory fabric).

ASCENT is one of six research centers funded by the SRC’s Joint University Microelectronics Program (JUMP), which represents a consortium of industrial participants and the Defense Advanced Research Projects Agency (DARPA). Information about the SRC can be found at https://www.src.org/.

ASCENT is a collaboration of the following Universities:

Congratulations to Prof. Robert W. Dutton

The 2020 IEEE EDS Celebrated Member and Esteemed EDS Alumni

Dr. Dutton received his degrees from the University of California, Berkeley, and currently instructs electrical engineering at Stanford University. Current members of EDS take pride in the Celebrated Members' accomplishments, drawing from their achievements as inspiration to advance and achieve success in various fields. The award presentation will be held virtually during the 2020 IEDM in December [read more...]

ROBERT W. DUTTON

Robert W. Dutton received the B.S., M.S., and Ph.D. in Electrical Engineering degrees from the University of California, Berkeley, in 1966, 1967, and 1970, respectively. 

He is currently Robert and Barbara Kleist Professor of Electrical Engineering at Stanford University, and Associate Chair for Undergraduate Education. He has held summer staff positions at Fairchild, Bell Telephone Laboratories, Hewlett‐Packard, IBM Research, and Matsushita during 1967, 1973, 1975, 1977, and 1988 respectively. His research interests focus on integrated circuit process, device, and circuit technologies, especially the use of computer‐aided design (CAD) and parallel computational methods. He has published more than 200 journal articles and graduated more than four dozen doctorate students. 

Dr. Dutton was Editor of the IEEE Transactions on Computer Aided Design from 1984 to 1986, the winner of the 1987 IEEE J. J. Ebers Award, 1988 Guggenheim Fellowship to study in Japan, elected to the National Academy of Engineering in 1991, 1996 Jack A. Morton Award, 2000 C&C Prize Japan, University Researcher Award, Semiconductor Industry Association (2000), Phil Kaufman Award, Electronic Design Automation Consortium (2006), and 2014 Bass University Fellow in Undergraduate Education Program, Stanford University.

Remember when the keyboard was the computer?

and in less than four (4) decades we are back: 

FROM Oric1:
a CPU (MOS 6502A @ 1 MHz) with 16KB ROM/48KB, Sound: AY-3-8912, Graphics: 40×28 text characters/ 240×200 pixels, 8 colours and simple connectivity - tape recorder I/O, Centronics compatible printer port, RGB video out, RF out, expansion port
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a quad-core 64-bit @ 1.8GHz CPU Cortex-A72 (ARM v8) 64-bit (BCM2711) with 4GB RAM (LPDDR4-3200), wireless networking (IEEE 802.11b/g/n/ac wireless LAN, Bluetooth 5.0, BLE), dual-display output and 4K video playback it is ideal for surfing the web, creating and editing documents, watching videos, and learning to program using the Raspberry Pi
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[paper] SPICE Compact Model for Schottky-Barrier FETs

Sheikh Aamir Ahsan, Member, IEEE, Shivendra Kumar Singh, Chandan Yadav, Member, IEEE, Enrique G. Marín, Member, IEEE, Alexander Kloes, Senior Member, IEEE

and Mike Schwarz, Senior Member, IEEE

A Comprehensive Physics-Based Current–Voltage SPICE Compact Model 

for 2-D-Material-Based Top-Contact Bottom-Gated Schottky-Barrier FETs

IEEE Transactions on Electron Devices, vol. 67, no. 11, pp. 5188-5195, Nov. 2020

DOI: 10.1109/TED.2020.3020900

Abstract: In this article, we report the development of a novel physics-based analytical model for explaining the current–voltage relationship in Schottky barrier (SB) 2D material field effect transistors (FETs). The model has at its core the calculation of the surface-potential (SP) which is accomplished by invoking 2-D density of states in conjunction with Fermi–Dirac (FD) distribution for electron and hole statistics. The explicit computation for the SP, carried out using the Lambert-W function together with Halley’s method, is used to construct the SP-based band-diagram for realizing the transparency of the SBs. Thereafter, the ambipolar current is derived in terms of the electron and hole injection phenomena the thermionic emission and Fowler–Nordheim tunneling mechanisms at the SB contacts. Furthermore, drift-diffusion current is derived in terms of the SP and incorporated in the model to account for the scattering in the intrinsic 2D channel. Finally, the Verilog-A model is validated against experimental IV data reported in the literature for two different 2D material systems. This is the first demonstration of an explicit SP-based SPICE model for ambipolar SB-2-D-FETs that is simultaneously built on tunneling-emission and driftdiffusion formalisms.

Fig: (a) Band-diagram sketched along positive y-direction underneath the source electrode. Blue and black lines represent bands before and after applying Vgs. (b) ψ-based diagram sketched along positive x, constructed after calculating ψs and ψd. The geometrical screening length λ is given by λ ≈ (tox t2D)^1/2.

Acknowledgement: This work was supported in part by the National Project Implementation Unit (NPIU) through the third phase of Technical Education Quality Improvement Programme (TEQIP-III) Project and in part by DST-SERB Startup Research Grant under Award SRG/2019/001122.

[paper] Process Induced Vt Variability

Mandar S. Bhoir, Member, IEEE, Thomas Chiarella, Jerome Mitard, Naoto Horiguchi, Member, IEEE, and Nihar Ranjan Mohapatra, Senior Member, IEEE

Vt Extraction Methodologies Influence Process Induced Vt Variability:

Does This Fact Still Hold for Advanced Technology Nodes? 

IEEE Transactions on Electron Devices, vol. 67, no. 11, pp. 4691-4695, Nov. 2020

DOI: 10.1109/TED.2020.3025750.

Abstract: In this work, we have investigated the influence of Vt extraction procedure on overall Vt variability of sub-10 nm Wfin FinFETs. Using six different Vt extraction techniques (These are 1) constant current (CC) technique, 2) extrapolation in linear regime [ELR, also known as maximum trans-conductance (gm)] technique, 3) trans-conductance extrapolation (TCE) technique, 4) second-derivative (SD) technique, 5) ratio method (RM); and 6) transition method (TM) [1]) we have experimentally demonstrated that the Vt variability is independent of Vt extraction procedure (unlike reported earlier). Furthermore, through systematic evaluation on commonly used Vt extraction techniques, the physics behind this anomalous behavior is investigated. It is shown that the significant variation in metal gate work-function and gate dielectric charges in advanced CMOS nodes is mainly responsible for this behavior. This claim is further validated for FinFETs with deeply scaled fin-width and effective oxide thickness (EOT).

Fig: (a) Schematic illustration of different process-variability sources in FinFET; 

(b)Transfer characteristics for FinFETs with similar Vt, CC but different RSD.

These FinFETs have different Vt, ELR because of RSD induced gm, max variations

Acknowleegement: This work was supported in part by the Visvesvaraya Ph.D. Scheme, MeitY, Government of India MEITY-PHD-250 and in part by the Horizon 2020 ASCENT EU Project (Access to European Nanoelectronics Network) under Project 654384.

References:
[1] A. Ortiz-Conde, F. G. Sánche, J. J. Liou, A. Cerdeira, M. Estrada, and Y. Yue, “A review of recent MOSFET threshold voltage extraction methods,” Microelectron. Rel., vol. 42, no. 4, pp. 583—596, 2002, doi: 10.1016/S0026-2714(02)00027-6

Engineers at #PSU have demonstrated an #analog non-volatile #memory that can operate as a close mimic of the #synapse within the brain. https://t.co/fpykOONXAf #semi https://t.co/eHbD4Uez0a

Engineers at #PSU have demonstrated an #analog non-volatile #memory that can operate as a close mimic of the #synapse within the brain.https://t.co/fpykOONXAf#semi pic.twitter.com/eHbD4Uez0a

— Wladek Grabinski (@wladek60) November 2, 2020

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November 02, 2020 at 01:50PM
via IFTTT

#TSMC to Build Fab in #Arizona and They are #Hiring! https://t.co/AtMOY6j3ox #semi https://t.co/zfWFCKx3JT

#TSMC to Build Fab in #Arizona and They are #Hiring! https://t.co/AtMOY6j3ox #semi pic.twitter.com/zfWFCKx3JT

— Wladek Grabinski (@wladek60) November 2, 2020

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November 02, 2020 at 11:22AM
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Video Tutorial: What is Verilog-A

Video Tutorial: What is Verilog-A

Verilog-A is a behavioural modelling language for analog circuits from the Verilog Family. It is the subset of Verilog-AMS. Verilog-A HDL is derived from the IEEE 1364 Verilog HDL specification. The intent of Verilog-A HDL is to let designers of analog systems and integrated circuits create and use modules that encapsulate high-level behavioural descriptions as well as structural descriptions of systems and components.

Reference: 

[1] OVI Verilog-A LRM , 1996

[2] https://literature.cdn.keysight.com/litweb/pdf/ads2004a/pdf/verilogaref.pdf

[3] A New Approach to Compact Semiconductor device Modelling with Qucs Verilog-A analog module synthesis, M.E Brinson & V Kuznetsov, International Journal of Numnerical Mdelling, 2015

[4] https://github.com/cogenda/VA-BSIM48/blob/master/bsim4_release.va

[PhD Thesis] III-V MOS-HEMTs for 100-340GHz Communications Systems

UNIVERSITY OF CALIFORNIA

Santa Barbara

III-V In_xGa_1-xAs / InP MOS-HEMTs for 100-340GHz Communications Systems

A dissertation for PhD degree in Electrical and Computer Engineering

by Brian David Markman

Abstract: This work summarizes the efforts made to extend the current gain cutoff frequency of InP based FET technologies beyond 1THz. Incorporation of a metal-oxide-semiconductor field effect transistor (MOSFET) at the intrinsic Gate Insulator-Channel interface of a standard high electron mobility transistor (HEMT) has enabled increased g_m,i by increasing the gate insulator capacitance density for a given gate current leakage density. Reduction of RS,TLM from 110 Ω.μm to 75Ω.μm and Ron(0) from 160Ω.μm to 120Ω.μm was achieved by removing/thinning the wide bandgap modulation doped link regions beneath the highly doped contact layers. Process repeatability was improved by developing a gate metal first process and D_it was improved by inclusion of a post-metal H₂ anneal. In_xGa_1-xAs / InAs composite quantum wells clad with both InP and In_xAl_1-xAs were developed for high charge density and low sheet resistance to minimize source resistance. 

Figure a) InP-based HEMT b) III-V DC optimized MOSFET c) proposed InP-based MOS-HEMT

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[Citation] Markman, B. D. (2020). III-V In_xGa_1-xAs / InP MOS-HEMTs for 100-340GHz Communications Systems. UC Santa Barbara. ProQuest ID: Markman_ucsb_0035D_14853. Merritt ID: ark:/13030/m5v4681j. Retrieved from https://escholarship.org/uc/item/6st812pb

#Congratulations to Dr. Arokia Nathan J.J. Ebers Award winner

#Congratulations to 2020 #IEEE #ElectronDevicesSociety J.J. Ebers Award winner, Dr. Arokia Nathan @IEEEorg @IEEEAwards @Cambridge_Uni #semi https://t.co/zQ5YIDm3wl

— Wladek Grabinski (@wladek60) October 29, 2020

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October 29, 2020 at 08:49AM
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Fwd: Patrick Fay DL - III-N Nanowire FETs for Low-Power Applications

Patrick Fay DL - III-N Nanowire FETs for Low-Power Application

The EDS Germany Chapter and NanoP proudly presents Patrick Fay from University of Notre Dame, Indiana, USA
for a Distinguished Lecture on "III-N Nanowire FETs for Low-Power Applications". The lecture will be held on
23th November 2020 at 3pm Berlin time.  To view complete details for this event, click here to view the announcement

Date and Time

• Date: 23 Nov 2020
• Time: 03:00 PM to 04:00 PM
• All times are Europe/Berlin
• Add Event to Calendar
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Location

The Distiguished Lecture will be held via Zoom. Login information provided before the event and requires registration.

• Virtual
• Germany

Hosts

• Germany Section Chapter, ED15
• Co-sponsored by NanoP, Technische Hochschule Mittelhessen - University of Applied Sciences

Registration <https://events.vtools.ieee.org/m/245747>

• Starts 29 October 2020 08:00 AM
• Ends 21 November 2020 12:00 AM
• All times are Europe/Berlin
• No Admission Charge