Video Tutorial: What is Verilog-A

Video Tutorial: What is Verilog-A

Verilog-A is a behavioural modelling language for analog circuits from the Verilog Family. It is the subset of Verilog-AMS. Verilog-A HDL is derived from the IEEE 1364 Verilog HDL specification. The intent of Verilog-A HDL is to let designers of analog systems and integrated circuits create and use modules that encapsulate high-level behavioural descriptions as well as structural descriptions of systems and components.

Reference: 

[1] OVI Verilog-A LRM , 1996

[2] https://literature.cdn.keysight.com/litweb/pdf/ads2004a/pdf/verilogaref.pdf

[3] A New Approach to Compact Semiconductor device Modelling with Qucs Verilog-A analog module synthesis, M.E Brinson & V Kuznetsov, International Journal of Numnerical Mdelling, 2015

[4] https://github.com/cogenda/VA-BSIM48/blob/master/bsim4_release.va