Showing posts with label CMOS technology scaling. Show all posts
Showing posts with label CMOS technology scaling. Show all posts

Nov 2, 2020

[paper] Process Induced Vt Variability

Mandar S. Bhoir, Member, IEEE, Thomas Chiarella, Jerome Mitard, Naoto Horiguchi, Member, IEEE, and Nihar Ranjan Mohapatra, Senior Member, IEEE
Vt Extraction Methodologies Influence Process Induced Vt Variability:
Does This Fact Still Hold for Advanced Technology Nodes? 
IEEE Transactions on Electron Devices, vol. 67, no. 11, pp. 4691-4695, Nov. 2020
DOI: 10.1109/TED.2020.3025750.

Abstract: In this work, we have investigated the influence of Vt extraction procedure on overall Vt variability of sub-10 nm Wfin FinFETs. Using six different Vt extraction techniques (These are 1) constant current (CC) technique, 2) extrapolation in linear regime [ELR, also known as maximum trans-conductance (gm)] technique, 3) trans-conductance extrapolation (TCE) technique, 4) second-derivative (SD) technique, 5) ratio method (RM); and 6) transition method (TM) [1]) we have experimentally demonstrated that the Vt variability is independent of Vt extraction procedure (unlike reported earlier). Furthermore, through systematic evaluation on commonly used Vt extraction techniques, the physics behind this anomalous behavior is investigated. It is shown that the significant variation in metal gate work-function and gate dielectric charges in advanced CMOS nodes is mainly responsible for this behavior. This claim is further validated for FinFETs with deeply scaled fin-width and effective oxide thickness (EOT).


Fig: (a) Schematic illustration of different process-variability sources in FinFET; 
(b)Transfer characteristics for FinFETs with similar Vt, CC but different RSD.
These FinFETs have different Vt, ELR because of RSD induced gm, max variations

Acknowleegement: This work was supported in part by the Visvesvaraya Ph.D. Scheme, MeitY, Government of India MEITY-PHD-250 and in part by the Horizon 2020 ASCENT EU Project (Access to European Nanoelectronics Network) under Project 654384.

References:
[1] A. Ortiz-Conde, F. G. Sánche, J. J. Liou, A. Cerdeira, M. Estrada, and Y. Yue, “A review of recent MOSFET threshold voltage extraction methods,” Microelectron. Rel., vol. 42, no. 4, pp. 583—596, 2002, doi: 10.1016/S0026-2714(02)00027-6