Showing posts with label Read-out circuit. Show all posts
Showing posts with label Read-out circuit. Show all posts

Nov 18, 2020

[paper] Verilog-A Ion Sensitive FET for pH Sensor

Megha Agrawal, Nidhi Agrawal, Alpana Agarwal and Anil K. Saini*
Modeling of Ion Sensitive Field Effect Transistor for pH Sensor using Verilog-A
 Recent Advancement in Communication System & Image Processing
RACISP-2012 at: BKBIET, Pilani

Thapar University, PATIALA – 147004, Punjab
*Central Electronics Engineering Research Institute, PILANI – 333031, Rajasthan

Abstract: ISFET semiconductor technology enables the design of true solid state pH sensor. An ISFET can be modeled by considering it as two fully uncoupled stages: an electronic stage i.e., the MOSFET which is the starting structure of the ISFET and an Electro-chemical stage i.e., the electrolyte–insulator interface which is pH dependent. This paper describes the modeling of ISFET for pH measurement using Verilog A which is compatible with cadence environment. Any change in pH directly affects the threshold voltage of ISFET. To measure this change in pH, ISFET is configured in such a way so that change in threshold voltage can be directly detected. For this purpose a sensing read-out has been designed using Gate complementary ISFET/MOSFET pair (CIMP) technique. Simulated result shows good linearity between output voltage of sensing readout circuit with pH variation for the range of 1 to12. The ISFET is thermally instable due to semiconductor properties and pH dependency on temperature, which in turn affects the pH reading of the solution at a temperature other than room temperature with slope of +0.69mV/0C, +1.25mV/0C and +1.60mV/0C respectively for pH= 4, for pH=7 and for pH=10.
Fig: a) n-channel ISFET structure and b) its equivalent electric circuit [ref]

Acknowledgment: The work is financially supported by Department of Information Technology, Ministry of Communication & Information Technology, Government of India, under SMDP-VLSI (Phase II) project.

[ref] Sergio Martinoia, Giuseppe Massobrio, “A Behavioral Macromodel of the ISFET in SPICE,” Sensors and Actuators B, Vol. 62, pp. 182–189, 2000

Appendix A

// Verilog-A Code for ISFET [ref]
`include "constants.vams"
`include "disciplines.vams"
module ISFET(ref,gm,ph);
inout ref,gm,ph;
electrical ref,gm,ph;
real EPH;
real T;
electrical node;
electrical x,y;
// PARAMETERS FOR ISFET
parameter real NAv = 6.023E26; //Avogadros constant(1/MOLE)
// ISFET geometrical parameters
parameter real DIHP =0.1E-9;
parameter real DOHP =0.3E-9;
//ISFET electrochemical parameters
parameter real KA = 15.8;
parameter real KB = 63.1E-9;
parameter real KN = 1E-10;
parameter real Nsil = 3.0E+18;
parameter real Nnit = 2.0E+18;
parameter real Cbulk = 0.1;
parameter real epso = 8.85E-12;
parameter real epsihp = 32; //relative permittivity of the Inner Helmholtz layer
parameter real epsohp = 32; //relative permittivity of the Outer Helmholtz layer
parameter real epsw = 78.5; //relative permittivity of the bulk electrolyte solution
//Reference-electrode electrochemical parameters
parameter real Eabs = 4.7; //absolute potential of the standard hydrogen electrode
parameter real Erel = 0.2;
parameter real Phim = 4.7; //work function of the metal back contact
parameter real Philj = 1E-3; //liquid-junction potential difference between the ref
solution and the electrolyte
parameter real Chieo = 3E-3; //surface dipole potential
real ET; //THERMAL COFFICIENT
real sq;
real CH, CD, CEQ, CB;
real Eref;

analog begin
T= $temperature;
ET= (`P_Q /(`P_K * T));
sq = sqrt(8*`P_EPS0*epsw*`P_K * T);
CB = (NAv*Cbulk);
CH = ((`P_EPS0*epsihp*epsohp) / (epsohp*DIHP + epsihp*DOHP));
CD = (sq*ET*0.5)*sqrt(CB);
CEQ = 1/(1/CD + 1/CH);
V(ref,node) <+ Eabs - Phim - Erel + Chieo + Philj;
Eref = V(ref,node);
V(x)<+ log(KA*KB)+4.6*V(ph);
V(y)<+ log(KA)+2.3*V(ph);
V(gm,node) <+ (`P_Q / CEQ) * (Nsil * ((limexp(-2 * V(gm,node) * ET)– limexp
(V(x))) / (limexp(-2 * V(gm,node) * ET) + limexp(V(y)) * limexp(-1 * V
(gm,node)*ET) + limexp(V(x)))) + Nnit*((limexp(-1 * V(gm,node)*ET))/(limexp(-1* V(gm,node)*ET)
+ (KN/KA) * limexp(V(y)))));
end
capacitor #(.c(CEQ)) Cq(node,gm);
resistor #(.r(1G)) RP1(x,gnd);
resistor #(.r(1G)) RP2(y,gnd);
resistor #(.r(1k)) RPH(ph,gnd);
endmodule