[paper] TFETs for sensitive THz detection

I. Gayduchenko^1,2, S.G. Xu^3,4, G. Alymov¹, M. Moskotin^2,1, I. Tretyakov⁵, T. Taniguchi⁶, K.Watanabe⁷, G. Goltsman⁸, A.K. Geim^3,4, G. Fedorov^1,2, D. Svintsov¹, and D.A. Bandurin^3,1

Tunnel field-effect transistors for sensitive terahertz detection

arXiv:2010.03040 (2020)

¹Moscow Institute of Physics and Technology (National Research University), Dolgoprudny 141700, Russia
²Physics Department, Moscow Pedagogical State University, Moscow, 119435, Russia
³School of Physics, University of Manchester, Oxford Road, Manchester M13 9PL, United Kingdom
⁴National Graphene Institute, University of Manchester, Manchester M13 9PL, United Kingdom
⁵Astro Space Center, Lebedev Physical Institute of the Russian Academy of Sciences, Moscow 117997, Russia
⁶International Center for Materials Nanoarchitectonics, National Institute of Material Science, Tsukuba 305-0044, Japan
⁷Research Center for Functional Materials, National Institute of Material Science, Tsukuba 305-0044, Japan
⁸National Research University Higher School of Economics, Moscow, 101000, Russia

Abstract: The rectification of high-frequency electromagnetic waves to direct currents is a crucial process for energy harvesting, beyond 5G wireless communications, ultra-fast science, and observational astronomy. As the radiation frequency is raised to the sub-terahertz (THz) domain, efficient ac-to-dc conversion by conventional electronics becomes increasingly challenging and requires alternative rectification protocols. Here we address this challenge by tunnel field-effect transistors made of dual-gated bilayer graphene (BLG). Taking advantage of BLG’s electrically tunable band structure, we create a lateral tunnel junction and couple it to a broadband antenna exposed to THz radiation. The incoming radiation is then down-converted by strongly non-linear interband tunneling mechanisms, resulting in exceptionally high-responsivity (exceeding 3kV/W) and low-noise (0.2pW/Hz−−−√)  detection at cryogenic temperatures. We demonstrate how the switching from intraband Ohmic to interband tunneling regime within a single detector can raise its responsivity by one order of magnitude, in agreement with the developed theory. Our work demonstrates an unexpected application of interband tunnel transistors for high-frequency detection and reveals bilayer graphene as one of the most promising platforms therefor.

Fig: Overview of THz detectors. NEP for THz detectors of various types plotted against the temperature at which they operate. Vertical error bars represent the spread of the detectors’ performance over the frequency range 0.1−2 THz. Horizontal error bars show the temperature range at which the detectors operate.  

Acknowledgements: This work was supported by the Russian Foundation for Basic Research within Grants No. 18-37-20058 and No. 18-29-20116. Experimental work of IG (photoresponse measurements) was supported by the Russian Foundation for Basic Research (grant 19-32-80028). We acknowledge support of the Russian Science Foundation grant No. 19-72-10156 (NEP analyses) and grant No.17-72-30036 (transport measurements). The work of GA and DS (theory of THz detection) was supported by grant # 16-19-10557 of the Russian Scientific Foundation. K.W. and T.T. acknowledge support from the Elemental Strategy Initiative conducted by the MEXT, Japan, Grant Number JPMXP0112101001, JSPS KAKENHI Grant Number JP20H00354 and the CREST(JPMJCR15F3), JST. The authors thank A. Lisauskas, W. Knap, A. I. Berdyugin and M.S. Shur for helpful discussions.

[paper] Compact Modeling of GaN HEMTs

Y. Chen et al., "Compact Modeling of THZ Photomixer Made from GaN HEMT," 2020 IEEE International Conference on Advances in Electrical Engineering and Computer Applications (AEECA), Dalian, China, 2020, pp. 484-489, doi: 10.1109/AEECA49918.2020.9213681.

Y. Chen et al., "A Surface Potential Based Compact Model for GaN HEMT I-V and CV Simulation," 2020 IEEE International Conference on Advances in Electrical Engineering and Computer Applications (AEECA), Dalian, China, 2020, pp. 490-495, doi: 10.1109/AEECA49918.2020.9213674.

A. Zhang et al., "Compact Modeling of Capacitance Components for GaN HEMTs," 2020 IEEE International Conference on Advances in Electrical Engineering and Computer Applications (AEECA), Dalian, China, 2020, pp. 505-511, doi: 10.1109/AEECA49918.2020.9213571.

FIG: Simplified GaN HEMT Structure

[chapter] Low-Voltage Analog IC Design

Deepika Gupta¹

Low-Voltage Analog Integrated Circuit Design

Nanoscale VLSI. Book series (ESIEE) (2020) pp 3-22

DOI: 10.1007/978-981-15-7937-0_1

¹Department of Electronics and Communication Engineering, IIIT Naya Raipur, India

Abstract: In this chapter, we review the challenges and effective design techniques for ultra-low-power analog integrated circuits. With the miniaturization, having low-power low-voltage mixed signal IC is essential to maintain the electric field in the device. This constraint presents bottleneck for the researchers to design robust analog circuits. Specifically, the low value of supply voltage with small technology influences many specifications of analog IC, e.g., power supply rejection, dynamic range and immunity to noise, etc. In addition, it also affects the ability of the MOS transistor to be operated in the strong inversion region. Note that with the technology reduction, power supply VDD is reducing but the threshold voltage VT is not decreasing proportionally to maintain low leakage current. However, this process reduces the overdrive voltage and limits the staking of transistors. In this case, the transistor can be made to work in weak inversion to work and reduce the power consumption. Further, reduction in VDD to achieve low-power consumption causes many other circuit-related issues such as PVT variations, degradation of dynamic range, mismatching in circuits element and differential paths. There have been many design methods developed for the ultra-low-power analog ICs. In this chapter, we will discuss some of the design techniques to reduce the power consumption in analog ICs. In addition, we will also discuss the basic building blocks of analog circuits with discussed design techniques. The charge-based EKV model can be a very suitable example of a MOS simulation model to be used in all inversion regions of transistor operations [Enz 2017]. In EKV model, the smallest number of core parameters is needed for the accurate behavioral modeling of transistor. Particularly, charge-based EKV model is beneficial for the analysis of analog circuits because it allows the analysis with simple calculations over different inversion regions. Hence, developing new device simulation models specific for analog circuit design is crucial.

Fig: Vth and Vdd scaling trend vs. Leff  [Zhao 2006]

References:

[Enz 2018] Enz C, Chicco F, Pezzotta A (2017) Nanoscale MOSFET modeling-part 1: the simplified EKV model for the design of low-power analog circuits. IEEE Solid-State Circuits Magazine 9(3):26–35

[Zhao 2006] Zhao W, Cao Y (2006) New generation of predictive technology model for sub-45 nm early design exploration. IEEE Trans Electron Devices 53(11):2816–2823

[paper] TCAD-Machine Learning Framework

Hiu Yung Wong¹ (Senior Member, IEEE), Ming Xiao², Boyan Wang², Yan Ka Chiu¹, Xiaodong Yan³, Jiahui Ma³, Kohei Sasaki⁴, Han Wang³ (Senior Member, IEEE)

and Yuhao Zhang² (Member, IEEE)

TCAD-Machine Learning Framework for Device Variation and Operating Temperature Analysis with Experimental Demonstration

IEEE J-EDS, vol. 8, pp. 992-1000, 2020

doi: 10.1109/JEDS.2020.3024669.

¹Department of Electrical Engineering, San Jose State University, San Jose, CA 95112, USA
²Virginia Polytechnic Institute, State University, Blacksburg, VA 24060, USA
³Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, CA 90089, USA
⁴Development Department, Novel Crystal Technology Inc., Sayama 3501328, Japan

Abstract: This work, for the first time, experimentally demonstrates a TCAD-Machine Learning (TCADML) framework to assist the analysis of device-to-device variation and operating (ambient) temperature without the need of physical quantities extraction. The ML algorithm used in this work is the Principal Component Analysis (PCA) followed by third order polynomial regression. After calibrated to limited ‘expensive’ experimental data, ‘low cost’ TCAD simulation is used to generate a large amount of device data to train the ML model. The ML was then used to identify the root cause of device variation and operating temperature from any given experimental current-voltage (I-V) characteristics. We applied this framework to study the ultra-wide-bandgap gallium oxide (Ga2O3) Schottky barrier diode (SBD), an emerging device technology that holds great promise for temperature sensing, RF, and power applications in harsh environments. After calibration, over 150,000 electrothermal TCAD simulations are performed with random variation of physical parameters (anode effective work function, drift layer doping, and drift layer thickness) and operating temperature. An ML model is trained using these TCAD data and we found 1,000-10,000 TCAD data can train an accurate machine. We show that without physical quantities extraction, performing PCA is essential for the TCAD trained ML model to be applicable to analyze experimental characteristics. The physical parameters and temperatures predicted by the ML model show good agreement with experimental analysis. Our TCAD-ML framework shows great promise to accelerate the development of new device technologies with a significantly more efficient process of material and device experimentation.

FIG: Flow chart diagram of the proposed TCAD-Machine Learning framework. All components are demonstrated in this article except the MLDatabase which stores previously trained ML algorithms.

Acknowledgment: The authors thank Dr. Pooya Jannaty of Cruise and Dr. Philip Leong of the University of Sydney for the discussion of ML algorithms. The experimental work is in part supported by the Southeastern Center for Electrical Engineering Education program and the High Density Integration industry mini-consortium of the Center for Power Electronics Systems at Virginia Tech.

[paper] Metamaterial for Wearable Applications

Kabir Hossain^1,2, Thennarasan Sabapathy^1,2, Muzammil Jusoh^1,2, Ping Jack Soh1^1,2 Ainur Fasihah Mohd Fazilah^1,2, Ahmad Ashraf Abdul Halim^1,2, N. S. Raghava³, Symon K. Podilchak⁴, Dominique Schreurs⁵, Qammer H. Abbasi⁶

ENG and NZRI Characteristics of Decagonal Shaped Metamaterial for Wearable Applications

International Conference on UK-China Emerging Technologies 

UCET, Glasgow, United Kingdom, 2020, pp. 1-4, 

doi: 10.1109/UCET51115.2020.9205409

¹Advanced Communication Engineering (ACE) Centre of Excellence, Universiti Malaysia Perlis, No 15 & 17, Jalan Tiga, Pengkalan Jaya Business Centre, 01000 Kangar, Perlis, Malaysia. 

²School of Computer and Communication Engineering, Universiti Malaysia Perlis, Kampus Alam UniMAP Pauh Putra, Arau 02600, Malaysia 

³Departments of Electronics and Communication Engineering, Delhi Technological University, India
⁴Institute of Digital Communications, School of Engineering, University of Edinburgh, EH9 3FB, UK
⁵ESAT-TELEMIC Research Division, KU Leuven, Kasteelpark Arenberg 10 Box 2444, 3001 Leuven, Belgium 

⁶James Watt School of Engineering, University of Glasgow, UK

Abstract: A decagonal-shaped split ring resonator metamaterial based on a wearable or textile-based material is presented in this work. Analysis and comparison of various structure sizes are compared considering a compact 6×6 mm2 metamaterial unit cell, in particular, where robust transmissionreflection (RTR) and Nicolson-Ross-Weir (NRW) methods have been performed to extract the effective metamaterial parameters. An investigation based on the RTR method indicated an average bandwidth of 1.39 GHz with a near-zero refractive index (NZRI) and a 2.35 GHz bandwidth when considering epsilon negative (ENG) characteristics. On the other hand, for the NRW method, approximately 0.95 GHz of NZRI bandwidth and 2.46 GHz of ENG bandwidth have been observed, respectively. These results are also within the ultrawideband (UWB) frequency range, suggesting that the proposed unit cell structure is suitable for textile UWB antennas, biomedical sensors, related wearable systems, and other wireless body area network communication systems.

Fig: The real NZRI values obtained using the RTR and NRW methods for different unit cell structures: (a) 1 1 × array, (b) 2 1× array, (c) 1 2 × array, and (d) 2 2 × array

Acknowledgment: The author would like to acknowledge the support from the Fundamental Research Grant Scheme (FRGS) under a grant number of FRGS/1/2019/TK04/UNIMAP/02/3 from the Ministry of Education Malaysia.

[paper] X-Parameters Based Characterization and Compact Modeling of SiGe HBT Linearity

[paper] G. Niu, Anni Zhang, Yiao Li, Huaiyuan Zhang, Andries Scholten, Marnix Willemsen, Ralf Pijper and L.F. Tiemeijer; X-Parameters Based Characterization and Compact Modeling of SiGe HBT Linearity; ECS Transactions 2020, Volume 98, Number 5 https://t.co/PzJnIjkFC8 #semi pic.twitter.com/7IAIkqfPjF

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Special IJHSES Issue on Advancements in Smart Grid Technologies

International Journal of High Speed Electronics and Systems

ISSN (print): 0129-1564 | ISSN (online): 1793-6438

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Call for Papers

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Special Issue on Advancements in Smart Grid Technologies

This special issue is on electrical power generation, transmission, distribution and utilization in smart grid, from the viewpoints of individual power system elements and their integration, interaction and technological advancement.

The special issue focuses on microelectronic systems, circuits, power control and soft computing techniques in smart grid. It includes, but are not limited to, the following:

• Renewable & Sustainable Energy Technologies
• Cloud-assisted smart grid architectures and development
• Internet-centric smart grid solutions
• Case studies on recent advances in smart grid and renewable energy system
• Information and communication technology for enhancing smart grid and renewable energy system
• Future of renewable energy sources in environmental protection
• Sustainable computational methods to evaluate the optimization of renewable energy systems
• Networking and data mining in smart grids for continuous sustainable development
• Threat, challenges & opportunity of integrating smart grid and renewable energy system
• Generation techniques ranging from advances in conventional electromechanical methods, through nuclear power generation, to renewable energy generation.
• A study on the smart grid and renewable energy system for reducing the complexity of power grids
• Distribution techniques, equipment development, and smart grids.
• Renewable power generation and clean energy technologies
• Distributed energy resources and storage
• Modern power grid devices, sensors and wireless technologies

Paper Submission and Review Schedule:

• First announcement: October. 12th 2020
• Submission Deadline: November30th 2020
• Final notification: January 10, 2020
• Publication Date: June 30th 2020

Camera ready articles should be sent to the Guest Editor for consideration. Please specify the research topic on the cover page.

IJHSES Editor-in-Chiefs:
Michael Shur, Rensselaer Polytechnic Institute (USA)
Wladek Grabinski, MOS-AK (EU)

Guest Editor:
Naresh Kumar Yadav, D.C.R.U.S.T, Murthal (India)

[paper] Flexible MO TFT for Analog Applications

Giuseppe Cantarella¹, Júlio Costa², Tilo Meister³, Koichi Ishida³, Corrado Carta³, Frank Ellinger³, Paolo Lugli¹, Niko Münzenrieder^1,2 and Luisa Petti¹

Review of recent trends in flexible metal oxide thin-film transistors for analog applications

Flexible and Printed Electronics 2020, Vol. 5, No. 3

DOI: 10.1088/2058-8585/aba79a

¹Faculty of Science and Technology, Free University of Bozen-Bolzano, 39100, Bozen, Italy
²Flexible Electronics Laboratory, University of Sussex, Brighton, BN1 9QT, United Kingdom
³Chair of Circuit Design and Network Theory, TU Dresden, 01069 Dresden, Germany

Abstract: Thanks to the extraordinary advances flexible electronics have experienced over the last decades, applications such as conformable active-matrix displays, ubiquitously integrated disposable flexible sensor nodes, wearable or textile-integrated systems, as well as imperceptible and transient implants are now reachable. To enable these applications, specialized analog circuits able to transmit and receive data, condition sensors' parameters, drive actuators or control powering devices are required. High-performance sensor conditioning, driving and transceiver circuits on a wide range of flexible substrates are therefore extremely important to develop. However, the currently available materials and processes compatible with mechanically flexible substrates impose massive limitations in terms of large-area uniformity, device dimensions' shrinkability and circuit design, challenging the realization of flexible analog systems. Among state-of-the-art technologies employing low-temperature fabrication processes, thin-film transistors (TFTs) based on metal oxide semiconductors represent the potentially best compromise in terms of prize, performance, technology maturity and capacity to realize complex systems. This is why metal oxide TFTs are nowadays widely used for flexible, light-weight, transparent, stretchable and bio-degradable analog circuits and systems. Here, we review the current trends of flexible metal oxide TFTs for analog applications. First, an introduction is given, where current challenges and requirements related to the realization of flexible analog circuits and systems are analysed. Additionally, TFT performance parameters and configurations are briefly revised. Then, the recent advances in the field of flexible metal oxide TFTs for analog applications are summarized. In particular, all reported approaches to reduce the channel length and improve the AC performance are shown. Next, the current state of flexible metal oxide TFT-based analog circuits is shown, discussing n-type only and complementary circuit configurations. The last topic of the review covers systems based on flexible metal oxide analog circuits. Finally, a conclusion is drawn and an outlook over the field is provided.

Figure: Overview of published works on flexible metal oxide TFT based circuits, indicating the minimum channel length of the devices, the operation frequency of the circuits, the effective supply voltage used, as well as the total TFT count. Only integrated circuits are included.

Acknowledgments: This work was partially supported by the DFG FFlexCom Priority Programme, Germany, through projects WISDOM II and Coordination Funds, under Grants 271795180 and 270774198. This work was also partially funded with internal funding of the Faculty of Science and Technology of the Free University of Bolzano-Bozen (project ”EYRE” RTD Call 2019).

[paper] Parameter Extraction in JFETs

Nikolaos Makris¹, Matthias Bucher¹, Member, IEEE, Loukas Chevas¹, Farzan Jazaeri²

and Jean-Michel Sallese²

Free Carrier Mobility, Series Resistance, and Threshold Voltage Extraction
in Junction FETs

in IEEE Transactions on Electron Devices, 

Special Section on ESSDERC/ESSCIRC 2020

DOI: 10.1109/TED.2020.3025841.

¹School of Electrical and Computer Engineering, TU Crete (GR)

²Ecole Polytechnique Fédérale de Lausanne, EPFL (CH)

Abstract: In this brief, extraction methods are proposed for determining the essential parameters of double gate junction field-effect transistors (FETs). First, a novel method for determining free carrier effective mobility, similar to a recently proposed method for MOSFETs, is developed. The same method is then extended to cover also the case when series resistance is present, while series resistance itself may be determined from the measurement from two FETs with different channel lengths. The key technological and design parameter is the threshold voltage, which may be unambiguously determined from the transconductance-to-current ratio with a constant-current method. The new methods are shown to be effective over a wide range of technical parameters, using technology computer-aided design simulations.

Fig: Extraction of carrier mobility for DG JFETs in linear region at 300K 

a) corresponding output conductance gds and constituents ∂gds/∂Vds and 2Qsc,d/b, and 

b) extracted mobility for long- and moderate-length devices close agreement with the constant, nonfield-dependent mobility (μ = 826 cm2/Vs) used in the TCAD simulations.

Aknowlegement: This work was supported in part by the INNOVATION-EL-Crete Project under Grant MIS 5002772. 

[paper] Compact Modeling in MFIS Negative-Capacitance FETs

N. Pandey and Y. S. Chauhan

Analytical Modeling of Short-Channel Effects in MFIS Negative-Capacitance FET

Including Quantum Confinement Effects

in IEEE TED (Early Access), DOI: 10.1109/TED.2020.3022002.

Abstract: An analytical 2-D model of double-gate metal-ferroelectric-insulator-semiconductor-negative-capacitance FET (MFIS-NCFET), using Green's function approach, in the subthreshold region, is presented in this article. The explicit solution of coupled 2-D Landau-Devonshire and Poisson equations is analytically derived. Subsequently, an analytical and explicit model of subthreshold slope is developed from potential functions. The developed model includes quantum-mechanical effects, which considers not only geometrical confinements but also electrical confinements. The analytical solution of a 2-D nonhomogeneous Poisson equation coupled with the 1-D Schrödinger equation is used to obtain the potential function in the channel. The impact of the ferroelectric thickness (tfe) on quantum confinement is also studied. We find that larger tfe reduces the quantum confinement effect. Therefore, as tfe increases, threshold voltage roll-off with the variation in Si-body thickness decreases.

Fig: Schematic of DG MFIS-NCFET.

Aknowegement: This work was supported in part by the Swarna Jayanti Fellowship under Grant DST/SJF/ETA-02/2017-18 and in part by the FIST Scheme of the Department of Science and Tech- nology under Grant SR/FST/ETII-072/2016. 

[paper] gm/ID-Based Sizing for Analog ICs

Tuotian Liao and Lihong Zhang

An LDE-Aware gm/ID-Based Hybrid Sizing Method for Analog Integrated Circuits

Analog Integrated Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1–1. doi:10.1109/tcad.2020.3025068 

Abstract: Layout-dependent effects (LDEs) have become increasingly more important in the synthesis of analog integrated circuits. In this paper, a two-phase hybrid sizing method for high performance analog circuits is proposed. It consists of gm/ID-based device characterization, circuit modeling, sensitivity-based constraints for LDEs, and mixed-integer nonlinear programming in the first phase, and many-objective evolutionary algorithm (many OEA) based sizing in the second phase. In the first phase, accurate device characterization is handled with little modeling effort thanks to the gm/ID design methodology. Then the LDE parameters that are linked to the normalized DC current are further optimized with the aid of sensitivity analysis. Thus, a variety of electrical, geometrical, and LDE-related constraints can be conveniently integrated into modeling of the sizing problem. In the second phase, the many OEA-based sizing refiner can further optimize the LDE parameters by using more detailed layout information via our proposed model. A new floor plan variation scheme is also applied to improve computation efficiency and enhance optimization effectiveness. The experimental results demonstrate high efficacy of our proposed methodology in LDE-aware analog sizing optimization.

Fig: Module-level of the LDE-aware gm/ID EA two-phase synthesis flow

Thanks to the contribution of the EKV model [1], inversion coefficient (IC) can be used to indicate the biasing inversion level of a MOSFET. This helped Binkley et al. [2] change the design freedom from the conventional W, L, and ID to IC, L, and ID. Since IC is related to DC bias, device geometry, and device characteristics (e.g., gm/ID), it can reflect performance tradeoff (e.g., intrinsic gain vs. bandwidth) of a single MOSFET. In [3], bias information rather than gm/ID parameters was set as variables, while a small-scale LUT was built to find MOSFET aspect ratio (i.e., W/L) and eventually W.

Aknowlegement: This work was supported in part by the Natural Sciences and Engineering Research Council of Canada (NSERC), Canada Foundation for Innovation (CFI), Research and Development Corporation (RDC) of Newfoundland and Labrador, and Memorial University of Newfoundland.

References:

1. C. Enz, F. Chicco, and A. Pezzotta, “Nanoscale MOSFET modeling: Part 1: The simplified EKV model for the design of low-power analog circuits,” IEEE Solid-State Circuits Mag., vol. 9, no. 3, pp. 26–35, 2017.
2. D. M. Binkley, C. E. Hopper, S.D. Tucker, B.C. Moss, J. M. Rochelle, and, D. P. Foty, “A CAD methodology for optimizing transistor current and sizing in analog CMOS design,” IEEE Trans. Comput-Aided Design Integr. Circuits Syst., vol. 22 no. 2, pp. 225-237, 2003.
3. C.-W. Lin, P.-D. Sue, Y.-T. Shyu, and S.-J. Chang, “A bias-driven approach for automated design of operational amplifiers,” in Proc. Int.

[paper] oTFT Charge-Based Variability Model

Aristeidis Nikolaou, Ghader Darbandy, Jakob Leise, Jakob Pruefer, James W. Borchert, Michael Geiger, Hagen Klauk, Benjamin Iñiguez, Fellow, IEEE,

and Alexander Kloes, Senior Member, IEEE

Charge-Based Model for the Drain-Current Variability in Organic Thin-Film Transistors 

Due to Carrier-Number and CorrelatedMobility Fluctuation

in IEEE TED (early access), DOI: 10.1109/TED.2020.3018694.

Abstract: In this study, a consistent analytical chargebased model for the bias-dependent variability of the drain current of organic thin-film transistors is presented. The proposed model combines both charge-carrier-numberfluctuation effects and correlated-mobility-fluctuation effects to predict the drain-current variation and is verified using experimental data acquired from a statistical population of organic transistors with various channel dimensions, fabricated on flexible polymeric substrates in the coplanar or the staggered device architecture.

Fig: a) Cross section of the organic TFTs fabricated in the inverted coplanar (bottom-gate, bottom-contact) architecture. b) Transistor channel divided into a noisy element between positions x and x + δx and two noiseless transistors of channel lengths x and L − x, respectively. c) Small-signal representation.

Acknowledgment: This work was supported in part by the German Federal Ministry of Education and Research “SOMOFLEX” under Grant 13FH015IX6 and in part by the German Research Foundation (DFG) under Grant KL 1042/9-2 (SPP FFlexCom). The authors would like to thank AdMOS GmbH for support.

#CMC Releases #BSIM-Bulk

#Si2 Compact Model Coalition #CMC Releases Vital Updates to Industry Workhorse #BSIM-Bulk https://t.co/mOLZqWAJvr #semi pic.twitter.com/oniRTGv8zZ

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[paper] Ion-Gated Transistors

Ion-Gated Transistor: An Enabler for Sensing and Computing Integration

Xianbao Bu, Han Xu, Dashan Shang, Yue Li, Hangbing Lv, and Qi Liu

Advanced Intelligent Systems, p.2000156.

DOI: 10.1002/aisy.202000156

Abstract: With the rapid development of the Internet of Things, the amount of data we involved in our daily life is growing exponentially, which poses significant challenges for data processing and transmission to the conventional terminal sensors that passively acquire external data. Inspired by biological sensory nervous systems, building artificial intelligent sensory systems with both sensing and computing capability is regarded as a promising way to address these challenges, by which the acquired data can be preprocessed locally and timely before transmitting them to the remote server for further processing. Ion-gated transistors (IGTs), which have been widely used in sensors and have been recently investigated for neuromorphic computing, exhibit great potential in this domain. Herein, the essential operation principles, device structures, and electrical characteristics of IGT are introduced, and the recent developments in biosensors, neuromorphic computing, and intelligent sensors with near-sensor computing and in-sensor computing modes are summarized. To conclude, the current challenges and future development of IGT for intelligent sensory systems are presented.

Fig: (a) Optical micrograph displaying the top view of an individual IGT (top right) and IGT array conforming to the surface of a human hand (bottom left). (b) Sample traces of in vivo signals acquired by IGTs, reflecting the wide span of frequency and amplitude characteristics.  

Acknowledgements: X.B. and H.X. contributed equally to this work. This work was supported by the National Key R&D Program of China under grant no. 2018YFA0701500; the National Natural Science Foundation of China under grant nos. 61874138, 61821091, 61825404, 61732020, and 61851402; the Strategic Priority Research Program of the Chinese Academy of Sciences under grant no. XDB44000000; Major Scientific Research Project of Zhejiang Lab (grant no. 2019KC0AD02); and Beijing Academy of Artificial Intelligence (BAAI).

[paper] TFT Compact Model of AMOLEDs Image‐Retention

A Novel Charge Based TFT Compact Model Applicable 

to Image‐Retention Simulation of AMOLEDs

Genshiro Kawachi 

Tianma Japan Ltd., Kanagawa, Japan

SID Symposium Digest of Technical Papers, 51(1), 1390–1393. 

P‐193: Late‐News‐Poster; First published: 25 September 2020

DOI: 10.1002/sdtp.14145

Abstract: A novel TFT compact model based on surface potential and charge calculations has been developed. Two kinds of non‐quasi‐static (NQS) models are included to describe the transient effects of TFTs. Appling the new model, accurate simulation of image retention phenomena in AMOLEDs was realized.

Fig: Transient response of a 2T1C pixel circuit (a) after switching from black to gray level: (b) simulation assuming a distributed τ_NQS model and measured results are compared.

Free Webinar on @SPICE Simulation - Semiwiki https://t.co/r857oMaZjE #semi https://t.co/A867NuzVX3

Free Webinar on @SPICE Simulation - Semiwiki https://t.co/r857oMaZjE #semi pic.twitter.com/A867NuzVX3

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Spin-On Memory: Cerfe Labs spins out from Arm https://t.co/M9uk3GBKtG #semi https://t.co/jPr109ZlXt

Spin-On Memory: Cerfe Labs spins out from Arm https://t.co/M9uk3GBKtG #semi pic.twitter.com/jPr109ZlXt

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#Renesas signs deal with #opensource #ARM competitor https://t.co/RqUc0Kal7G #semi https://t.co/qHRJ7dzvD9

#Renesas signs deal with #opensource #ARM competitor https://t.co/RqUc0Kal7G#semi pic.twitter.com/qHRJ7dzvD9

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Łukasiewicz-Instytut Mikroelektroniki i Fotoniki - will develop Polish electronics. The pillars of the new institute will be, as before: employees, equipment and technologies. #semi https://t.co/VYeKhDf8TC

Łukasiewicz-Instytut Mikroelektroniki i Fotoniki - will develop Polish electronics. The pillars of the new institute will be, as before: employees, equipment and technologies.#semi https://t.co/VYeKhDf8TC

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[thesis] RF UTBB FDSOI MOSFET

Vanbrabant, Martin

RF characterization of the back-gate contact on Fully Depleted SOI MOSFETs

http:// hdl.handle.net/2078.1/thesis:26763

Ecole polytechnique de Louvain, Université catholique de Louvain, 2020. 

Academic year 2019–2020: Master in Electrical Engineering

Prom.: Prof. Jean-Pierre Raskin

Readers: Denis Flandre, Valeriya Kilchytska, Lucas Nyssens, Martin Rack

Abstract: Thanks to the thin buried-oxide, the UTBB FDSOI technology with a highly doped region under the BOX is one of the main candidates for future RF applications. One of the most interesting feature of this technology is the possibility to tune the threshold voltage, compensate variability issues and improve the overall device performance. In this work, the impact of the back-gate bias is mainly studied on the threshold voltage and RF FoMs of the front and back-gates.

Figure: Reconstructed (dashed) vs initial (full) Re{Yij} insaturationat VDS=0.8V, VGS=0.8V and VB=0V for a 4-port device.

#Precursor is a mobile, open source electronics platform

#Precursor is a mobile, open source electronics platform. Similar to Raspberry Pi or an Arduino it can be transformed into an IoT gadget with just a couple breakout boards, some solder, and a bit of code for variety of DIY mobile applications https://t.co/XQkrw0coiK #semi pic.twitter.com/QtZup2uRgk

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#EPFL President M. Vetterli Takes On #Gender #Equality, COVID-19, and #Science Policy

#EPFL President Martin Vetterli Takes On #Gender #Equality, COVID-19, and #Science Policy https://t.co/Id0pjw1MHN #semi pic.twitter.com/MifKfRHe7B

— Wladek Grabinski (@wladek60) September 28, 2020

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What is #FOSS? What is #OpenSource?

Linux Jargon Buster: What is #FOSS (Free and Open Source Software)? What is #OpenSource? https://t.co/BdVZucwpO4 #semi pic.twitter.com/BwLlHWbJIB

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ASCENT+ project

ASCENT+ project "Access to European Infrastructure for Nanoelectronics​" coordinated by #Tyndall National Institute (SINANO member) https://t.co/Nvc2UIUt86 #Semi pic.twitter.com/6bc4VlV1WN

— Wladek Grabinski (@wladek60) September 25, 2020

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#Opensource chip tech #RISC-V

#Opensource chip tech #RISC-V could be a major #beneficiary of Arm's $40 billion sale to Nvidia https://t.co/WwYt79AmrU pic.twitter.com/SMwZuPD9xx

— Wladek Grabinski (@wladek60) September 25, 2020

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[paper] Ultra-High Voltage SiC IGBT

Wide-Range Prediction of Ultra-High Voltage SiC IGBT Static Performance

Using Calibrated TCAD Model

Daniel Johannesson^1,2, Keijo Jacobs¹, Staffan Norrga¹, Anders Hallén³, 

Muhammad Nawaz² and Hans-Peter Nee^1,2

Materials Science Forum Submitted: 2019-09-19

ISSN: 1662-9752, Vol. 1004, pp 911-916  

DOI:10.4028/www.scientific.net/MSF.1004.911

¹Division of Electric Power and Energy Systems, KTH , Sweden
²ABB Corporate Research, Västerås, Sweden
³Division of Electronics, KTH, Sweden

Abstract: In this paper, a technology computer-aided design (TCAD) model of a silicon carbide (SiC) insulated-gate bipolar transistor (IGBT) has been calibrated against previously reported experimental data. The calibrated TCAD model has been used to predict the static performance of theoretical SiC IGBTs with ultra-high blocking voltage capabilities in the range of 20-50 kV. The simulation results of transfer characteristics, IC-VGE, forward characteristics, IC-VCE, and blocking voltage characteristics are studied. The threshold voltage is approximately 5 V, and the forward voltage drop is ranging from VF = 4.2-10.0 V at IC = 20 A, using a charge carrier lifetime of τA = 20 μs. Furthermore, the forward voltage drop impact for different process dependent parameters (i.e., carrier lifetimes, mobility/scattering and trap related defects) and junction temperature are investigated in a parametric sensitivity analysis. The wide-range simulation results may be used as an input to facilitate high power converter design and evaluation. In this case, the TCAD simulated static characteristics of SiC IGBTs is compared to silicon (Si) IGBTs in a modular multilevel converter in a general highpower application. The results indicate several benefits and lower conduction energy losses using ultra-high voltage SiC IGBTs compared to Si IGBTs.

Fig: 4H-SiC IGBT structure implemented in 2D TCAD simulator

Acknowledgment This work was funded through SweGRIDS, by the Swedish Energy Agency and ABB.

[paper] Multi-Bridge-Channel Field Effect Transistor

Leakage Performance Improvement in Multi-Bridge-Channel Field Effect Transistor

(MBCFET) by Adding Core Insulator Layer 

Saehoon Joung^1,2, Student Member, IEEE and SoYoung Kim², Senior Member, IEEE 

SISPAD 2019 

DOI:10.1109/sispad.2019.8870498 

¹Samsung Electronics Co. Foundry Division, Yield Enhancement, Process Integration Engineering Group, Ltd Kiheung, Republic of Korea
²College of Information and Communication Engineering,Sungkyunkwan University, Suwon,Gyeounggi-do, Republic of Korea

Abstract: Altering from existing planar devices to FinFETs has revolutionized device performance, but demands of leakage and gate controllability are increasing relentlessly. Gate all around field effect transistor (GAAFET) is expected to be the next-generation device that meets these needs. This paper suggests a way to improve the gate electrostatic characteristics by adding an oxidation process to the conventional multi-bridgechannel field effect transistor (MBCFET) process. The main advantage of the proposed method is that a device with ultimate electrostatic properties can be implemented without changing the complex and expensive photo-patterning. In the proposed device, the immunity of short channel effects is enhanced in a single transistor. And the performance of ring oscillator (RO) and SRAM was confirmed to be improved by TCAD mixed-mode simulation.

FIG: MBCFET Process Flow Comparison 

 

Acknowledgement: This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No. NRF-2017R1A2B2003240). The TCAD tools were supported by the IC Design Education Center (IDEC).

[mos-ak] Fwd: MOS-AK / IEEE-EDS-MQ / SSB-MOS Workshops at THM - Deadline extended

Dear colleagues and friends, 

please note that the registration deadline for the

Joint Spring MOS-AK Workshop and 

Symposium on Schottky Barrier MOS (SB-MOS) devices with 

IEEE EDS Mini-Colloquium on „Non-conventional Devices and Technologies" 

has been extended. 

The event hosted by THM will take place in Zoom as live presentations Sept. 29 to Oct. 1. 

Please register until Sept. 25 by use of IEEE vTools: 

https://meetings.vtools.ieee.org/m/205571
The registration is for free. 

Preliminary program: 

https://ssbmos.blogspot.com/p/programm-2020.html and 

http://www.mos-ak.org/giessen_2020

Registered attendees will receive the Zoom link for the event a few days before via email from vTools.

Important new dates: 
1st Event Announcement: Aug. 2020 
2nd Event Announcement: Sept. 2020 
Final Workshop Program: Sept. 2020
Registration deadline (extended): Sept. 25, 2020
"Spring" MOS-AK Workshop: Sept. 29/30, 2020 
IEEE MQ: Sept. 30/Oct. 1, 2020
Symposium SB-MOS devices: Oct. 1, 2020

Best regards

Alexander Kloes

_____________________________________________________________

Prof. Dr.-Ing. Alexander Kloes

 

Technische Hochschule Mittelhessen - University of Applied Sciences

Department Electrical Engineering and Information Technology

Spokesperson of Competence Center Nanotechnology and Photonics

Director of Doctoral Theses at Universitat Rovira i Virgili, Tarragona

Wiesenstrasse 14

D-35390 Giessen

Germany

E-mail: alexander.kloes@ei.thm.de

Web: go.thm.de/dmrg-en and www.thm.de

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#TSMC's development of #2nm process technology, which is already out of its pathfinding mode, is ahead of schedule, according to industry sources https://t.co/7jiFBRomRy #semi https://t.co/ieDnhSHxZh

#TSMC's development of #2nm process technology, which is already out of its pathfinding mode, is ahead of schedule, according to industry sources https://t.co/7jiFBRomRy #semi pic.twitter.com/ieDnhSHxZh

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[paper] 2D Charge Density Wave Phases

Machine-Intelligence-Driven High-Throughput Prediction of 2D Charge Density Wave Phases

Arnab Kabiraj and Santanu Mahapatra*

J. Phys. Chem. Lett. 2020, 11, 15, 6291–6298

Publication Date:July 22, 2020

DOI: 10.1021/acs.jpclett.0c01846

*Nano-Scale Device Research Laboratory, IISc Bangalore, India

Abstract: Charge density wave (CDW) materials are an important subclass of two-dimensional materials exhibiting significant resistivity switching with the application of external energy. However, the scarcity of such materials impedes their practical applications in nanoelectronics. Here we combine a first-principles-based structure-searching technique and unsupervised machine learning to develop a fully automated high-throughput computational framework, which identifies CDW phases from a unit cell with inherited Kohn anomaly. The proposed methodology not only rediscovers the known CDW phases but also predicts a host of easily exfoliable CDW materials (30 materials and 114 phases) along with associated electronic structures. Among many promising candidates, we pay special attention to ZrTiSe4 and conduct a comprehensive analysis to gain insight into the Fermi surface nesting, which causes significant semiconducting gap opening in its CDW phase. Our findings could provide useful guidelines for experimentalists.

Fig: Top view of TaSe₂-H 3×3_ɸ-1.

Si2 VAMPyRE: compact model parser and checker

Si2 #Compact #Model #Coalition Offers VAMPyRE, the software is a standalone compact model parser and checker written in Python, to Members and Developers https://t.co/vPQWlcQ99l pic.twitter.com/gbUq5nBFOA

— Wladek Grabinski (@wladek60) September 21, 2020

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[tutorial] next generation 3D nano device simulator

Single-electron transistor - laterally defined quantum dot - 3D Tutorial

Stefan Birner

https://www.nextnano.com

Single-electron transistor - laterally defined quantum dot In this tutorial, we simulate an AlGaAs/GaAs heterostructure grown along the z direction. This structure leads to a two-dimensional electron gas (2DEG). By appying a gate voltage on top of the structure in the (x,y) plane, one is able to deplete the 2DEG and a laterally defined QD is formed. By adjusting the gate voltage, one is able to tune the number of electrons that are inside the QD.

This figure shows the conduction band edge Ec(x,y) and the electron density n(x,y) for the 2DEG plane, i.e. at z = 8 nm below the GaAs/AlGaAs heterojuntion. The geometry of the top gates is indicated by the blue regions. The following figure shows the calculated conduction band edge and the electron density of the heterostructure. The results are similar to Fig. 4 in paper [1].

The following figure shows two 2D slices through the lateral (x,y) plane at a distance of 8 nm below the AlGaAs/GaAs interface. In the middle, the electron density is shown. The electron density has been calculated classically. At the bottom, the conduction band edge is shown. The results are similar to Fig. 5 in paper [1]. At the top, the four gates are shown.

REF:

[1] A. Scholze, A. Schenk, W. Fichtner; Single-Electron Device Simulation; IEEE TED 47, 1811 (2000)

[paper] OTFTs in Mechanical Sensors

Organic Thin Film Transistors in Mechanical Sensors 

Zachary A. Lamport, Marco Roberto Cavallari^2,3, Kevin A. Kam, 

Christine K. McGinn, Caroline Yu, and Ioannis Kymissis

DOI: 10.1002/adfm.202004700

¹Department of Electrical Engineering, Columbia University, USA
²Departamento de Engenharia de Sistemas Eletrônicos, EPU de São Paulo, Brazil
³Department of Renewable Energies. UNILA, Brazil

Abstract: The marriage of organic thin-film transistors (OTFTs) and flexible mechanical sensors has enabled previously restricted applications to become a reality. Counterintuitively, the addition of an OTFT at each sensing element can reduce the overall complexity so that large-area, low-noise sensors can be fabricated. The best-performing instance of this is the active matrix, used in display applications for many of the same reasons, and nearly any type of flexible mechanical sensor can be incorporated into these structures. In this Progress Report, some of the flexible sensor devices that have taken advantage of these mechanical properties are highlighted, examining the advantages that OTFTs offer in the hybrid integration of local amplification and switching. In particular, the current research on resistive pressure sensors, capacitive pressure sensors, resistive or piezoresistive strain sensors, and piezoelectric sensors is identified and enumerated.

Fig: Suspended-gate FET: a) Schematic illustration of device geometry; b) electrical equivalent circuit; c) pressure response of ID at constant VDS = VGS = −60 V

Acknowledgements C.M. received funding from the National Science Foundation Graduate Research Fellowship Program (DGE—1644869). Z.L. thanks Corning and the NSF under STTR 1914013 for financial support.

[paper] Memristors in SPICE

Modeling networks of probabilistic memristors in SPICE

Vincent J. Dowling¹, Valeriy A. Slipko², Yuriy V. Pershin¹

arXiv:2009.05189v1 [cs.ET] 11 Sep 2020

DOI: 10.13164/re.2020.0001

¹Department of Physics and Astronomy, University of South Carolina, Columbia, SC 29208 USA
²Institute of Physics, Opole University, Opole 45-052, Poland

Abstract. Efficient simulation of probabilistic memristors and their networks requires novel modeling approaches. One major departure from the conventional memristor modeling is based on a master equation for the occupation probabilities of network states. In the present article, we show how to implement such master equations in SPICE. In the case studies, we simulate the dynamics of ac-driven probabilistic binary and multi-state memristors, and dc-driven networks of probabilistic binary and multi-state memristors. Our SPICE results are in perfect agreement with known analytical solutions. Examples of LTspice codes are included.

Fig: Ac-driven probabilistic binary memristor: (a) simulated circuit, (b) schematics of SPICE model, and (c) example of current-voltage curves found with SPICE simulations. The listing of SPICE model is given in Apendix.

Appendix: SPICE code examples

B1 0 p0 I=-gm(tau01,V01,V(Va))*V(p0)*u(V(Va))+gm(tau10,V10,-V(Va))*V(p1)*u(-V(Va))

B2 0 p1 I=gm(tau01,V01,V(Va))*V(p0)**u(V(Va))-gm(tau10,V10,-V(Va))*V(p1)**u(-V(Va))

C1 p0 0 1 IC=1

C2 p1 0 1 IC=.0

R2 Va 0 1k

R1 Va 0 10k

R3 VI 0 1k

B3 0 VI I=I(R1)*V(p0)+I(R2)*V(p1)

V1 Va 0 SINE(0 1 200 0 0 0 0)

.FUNC gm(x,y,z)1/(x*exp(-z/y))

.param tau01=3E5 V01=.05

.param tau10=3E5 V10=.05

.tran 0 .1 0.05 10E-7

.backanno

.end

[paper] Co-designing electronics with microfluidics

Remco van Erp, Reza Soleimanzadeh, Luca Nela, Georgios Kampitsis & Elison Matioli; Co-designing electronics with microfluidics for more sustainable cooling. Nature 585, 211–216 (2020). DOI: 10.1038/s41586-020-2666-1 https://t.co/WQ3ddWLuqp #paper pic.twitter.com/gqt3iVegwp

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[paper] Compact Model for MoS2 FETs

A physics-based compact model for MoS2 field-effect transistors

considering the band-tail effect and contact resistance

Yuan Liu¹, Jiawei Zeng², Zeqi Zhu¹, Xiao Dong² and WanLing Deng³

Japan Society of Applied Physics; Accepted Manuscript online 11 September 2020

¹Guangdong University of Technology, Guangzhou, Guangdong, CHINA

²Jinan University, Guangzhou, Guangdong, CHINA
³Electronic Engineering, Jinan University, Guangzhou, GuangDong, 510630, CHINA

Abstract: In this paper, we present a compact surface-potential-based drain current model in molybdenum disulfide (MoS2) field-effect transistors (FETs). Considering variable range hopping (VRH) transport via band-tail states in MoS2 transistors, an explicit solution for surface potential has been derived and it provides a good description over different regions of operation by comparisons with numerical data. Based on charge-sheet model (CSM) which applies to drift-diffusion transport, the current expression including contact resistance and velocity saturation effect is developed. Furthermore, the presented model is validated and shows a good agreement with experiment data for MoS2 FETs. Keywords: molybdenum disulfide (MoS2), surface potential, current expression.