Atomistic TNL TCAD Solutions

Greetings from Dr. Praveen Saxena. We wish good health to all recipients of the mail.  As a result of the significant disruption that is being caused by COVID-19 pandemic all around world and especially in India, everybody need to stay at home as preventive care and remain busy with some task. We are concerned about you and your family well-being. Please take care and stay safe.

 

 This is the best time to evaluate the Unmatched family of Innovative Atomistic TNL TCAD simulators. You may freely download the software from below link:

http://www.technextlab.com/login.php                                     

 

Register yourselves and download the TNL setup. Tech Next Lab will provide you 1- months licenses for all simulators free of cost along with technical support.

 

We are pleased to introduce in-house developed Unmatched family of Innovative Atomistic TNL TCAD simulators, including EpiGrow (Epitaxial Growth), FullBand (Material Characterization), HallMobility (Material Characterization), THz Spectroscopy (Material Characterization), and Monte Carlo Particle Device simulators (MCPDS).

 

All products are proprietary products of Tech Next Lab (P) Ltd. We provide instant technical and sales solution for the queries and feedback come from the customers. You may find more details about TNL TCAD tools on our website: www.technextlab.com

 

We may assure you that our simulators will surely help in expediting the most of semiconductor Technologies Developments and also benefits your students from teaching prospective. Few Publications:

 

For MOCVD epitaxial growth you may find more details:

https://www.sciencedirect.com/science/article/abs/pii/S0925838819329858

 

For GaN based technology for FET device applications:

https://link.springer.com/chapter/10.1007/978-981-15-5262-5_61

 

For Group-III nitrides and its alloys:

https://www.nature.com/articles/s41598-020-75588-3

 

Group II-VI Material Characterization:

https://link.springer.com/article/10.1007/s11664-021-08756-4

.

 

For Detector Application:

https://publications.drdo.gov.in/ojs/index.php/dsj/article/view/11177

https://link.springer.com/article/10.1007/s11082-020-02488-1

 

 

Feel free to write <info@technextlab.com> in case you have any query.

Looking forward to hear from you ASAP.

Best Regards,

Praveen

 

Atomistic TNL TCAD simulators:

 TNL Framework: TNL Framework includes family of innovative simulators based on atomistic level. It provides innovative technology solution to semiconductor industry. The technology development is expensive process and suffers with lot of technical challenges & issues. TNL framework is designed to innovate the semiconductor device designing. It accommodate atomistic based thin film growth simulator, full band simulator, material characterization simulator and Monte Carlo particle device simulator. 

 EpiGrow Simulator: EpiGrow simulator is world's first commercial innovative atomistic epitaxial growth simulator to grow thin film inside MBE/MOCVD reactors. EpiGrow simulator is powerful tool to trace atomistic thin and thick film growth inside reactors. Kinetic Monte Carlo algorithms keeps Randomness in adsorption, hopping & desorption processes. It offer cost economical solution for thin film growth technology even for nm thin monolayer. Capable to predict the initial conditions for Molecular Beam Epitaxy & Molecular Organic Chemical Vapor Deposition (MOCVD) reactors. Capable to calculate the lattice constant of monolayer, trace different types of defects, and strain. Optimizer provides flexibility to optimize initial conditions with EpiGrow Simulator and run design of experiments over the computer.

 TNL-FB Simulator:   Full Band Simulator is powerful tool, extends the empirical pseudopotential method to include semiconductors with the zincblende as well as wurtzite structures and simulates electronic band structures with appropriate pseudopotential form factors chosen from the reported reputed references for binary alloy semiconductor materials and interpolate the pseudopotential form factors for ternary alloy semiconductor materials to simulate the full electronic band structures of ternary materials. The bowing of band energies and their deformation potentials is included inside simulator in form of alloy disorder. Capable to simulate the full electronic band structures for the lattice constant of monolayer provided by users. Different types of physical parameters e.g. carrier velocity, effective mass and density of states can be easily tracable on the full electronic band structures of the chosen materials. Provides flexibility to users to chose lattice constant and analyse the full electronic band structures over computer.

 TNL-EM Simulator: Electron Mobility Simulator is powerful tool, simulates carriers transport on full energy band. The microscopic simulation of the motion of individual particles in the presence of the forces acting on them due to external fields as well as the internal fields of the crystal lattice and other charges in the system. In solids, such as semiconductors and metals, transport is known to be dominated by random scattering events due to impurities, lattice vibrations, etc. has been inputted through Monte Carlo technique, which randomize the momentum and energy of charge particles in time. Hence, stochastic techniques to model these random scattering events are particularly useful in describing transport in semiconductors, in particular the Monte Carlo method. Provides flexibility to users to initialize the carriers over full energy band and analyze the transport of carrier to simulate the ensemble velocity of carriers under external electromagnetic forces on computer.

 TNL-TS (THz Spectroscopy) Simulator is powerful tool to simulates motion of charged and interacting particles. The microscopic simulation of the motion of individual particles under the influence of the THz pulse as well as the internal fields of the crystal lattice and influence of other charges, lattice defects etc. In solids, such as semiconductors and metals, transport is known to be dominated by random scattering events due to impurities, lattice vibrations, etc., which randomize the momentum and energy of charge particles in time. The stochastic techniques to model these random scattering events are particularly useful in describing inter and intraband transitions of charge carriers in bulk & nonmaterial. The Monte Carlo technique use for solution of Boltzmann transport equation provides flexibility to users to initialize the carriers over many or particular band of the material and analyze the position, momentum, energy & other properties associated with motion of charged particles under influence of THz Pulses, frequencies ranging from few hundred gigahertz to several terahertz. THz Spectroscopy simulator has capabilities to simulate the microscopic conductivity of weakly confined, classical electrons in absence of depolarization effects without need of any approximations of fitting parameters to calibrate the Drude-Smith conductivities..

 TNL-PD Simulator: World's Fastest Monte Carlo Particle Device simulator includes transport model solution with a self -consistent Boltzmann-Poisson equation and a GUI based feature helps users to select device geometry and doping density in 2D and 3D. The different carrier scattering mechanisms has major influence on the performance of device output and dependent on the density of states (DOS) in each valley which can be accurately inputted through full band structure. The effect of equilibrium states of carrier before start of free flight of carrier has been incorporated in term of inclusion of depletion region through movement of the ensemble of carriers under influence of external electrostatic field obtained by solving the Poisson equation. The quantum confinement effect includes density gradient approach and effective potential approach for computation of quantum confinement effects on the carrier transport under influence of external forces. Particle Device Simulator (PDS) is exploited for unipolar as well as bipolar semiconductor technologies based devices including MOSFET, Multigate FETS, HEMT and P-N junction devices.

 

 

*******************************************

Dr. P. K. Saxena

CEO & CTO,

Tech Next Lab Pvt Ltd (TNL)

Near Nagar Nigam Office Zone-6,

Niwaz Ganj, Lucknow- 226 003 (INDIA)

 

Phone: (+91) 983 915 1284 / (+91) 9415893655

Fax: 0522 2258921

Email: info@technextlab.com 

Web: www.technextlab.com  

Skype ID: praveen.itbhu

Linkedin: https://www.linkedin.com/home?trk=nav_responsive_tab_home  

  

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[paper] Compact Model for SiC Power MOSFETs

Cristino Salcines¹, Sourabh Khandelwal² and Ingmar Kallfass¹ 

A Compact Model for SiC Power MOSFETs 

for Large Current and High Voltage Operation Conditions 

(2021) arXiv-2104. 

1 University of Stuttgart Stuttgart, Germany

2 Macquarie University Sydney, Australia  

Abstract: This work presents a physics based compact model for SiC power MOSFETs that accurately describes the I-V characteristics up to large voltages and currents. Charge-based formulations accounting for the different physics of SiC power MOSFETs are presented. The formulations account for the effect of the large SiC/SiO2 interface traps density characteristic of SiC MOSFETs and its dependence with temperature. The modeling of interface charge density is found to be necessary to describe the electrostatics of SiC power MOSFETs when operating at simultaneous high current and high voltage regions. The proposed compact model accurately fits the measurement data extracted of a 160 milli ohms, 1200V SiC power MOSFET in the complete IV plane from drain-voltage Vd = 5mV up to 800 V and current ranges from few mA to 30 A.

Fig: Output characteristics up to high current and high voltage in logarithmic scale for VGS = 6V to 20V in steps of 0.5V. Symbols are measurements and solid lines simulations of the proposed model. The logarithmic scale eases the visualization of both low and high VDS voltages in a single graph.

Quirk is a quantum circuit simulator, great for manipulating and exploring small quantum circuits. Quirk's visual style gives a reasonably intuitive feel of what is happening, state displays update in real time, and is fast and interactive https://t.co/y5Izitamco #semi https://t.co/mLo2ZlSQQb

Quirk is a quantum circuit simulator, great for manipulating and exploring small quantum circuits. Quirk's visual style gives a reasonably intuitive feel of what is happening, state displays update in real time, and is fast and interactive https://t.co/y5Izitamco #semi pic.twitter.com/mLo2ZlSQQb

— Wladek Grabinski (@wladek60) May 10, 2021

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May 10, 2021 at 11:40AM
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10th All-Russia MES-2021 Conference

10th All-Russia Science and Technology Conference

Problems of Advanced Micro- and Nanoelectronic Systems Development 

MES-2021

March - November 2021

Moscow | Zelenograd

MES-2021 is dedicated to urgent issues of design automation of microelectronic systems, SoC, IP-blocks and a new element base of micro-and nanoelectronics. These issues have been and remain actual to science and technology, as evidenced by the major topics of the Annual International Conference on CAD and the development of micro-and nanoelectronic devices. MES is the largest conference in the field of CAD microelectronics in Russia and CIS countries. Proceedings of the MES conference is included in HAC list (issue 23.03.2021, pos. 2017) of Russian scientific journals, where should be published the main results of the PhD and DSc theses.

The upcoming 10th MES-2021 conference will be held mainly in the correspondence format, starting on March 01, 2021, and it will be concluded with its plenary session in November 2021.

Key discussion topics

1. Theoretical aspects of micro-and nanoelectronic systems (MES).
2. Methods and tools of design automation for micro-and nanoelectronic circuits and systems (VLSI CAD).
3. Experience of development of digital, analog, digital to analog, radio functional blocks of VLSI.
4. Features of VLSI design for nanometer technologies.
5. SoCs for advanced radioelectronic equipment.
6. Exhibition and presentation of commercial products.

Fields of interest of the conference include (but is not limited to) the following topics of relevant studies of VLSI design and VLSI design automation techniques:

Design

1. Circuits and Systems based on nanometer technologies

2. Systems on Chip

3. Digital VLSI Design

4. Design of analog functional blocks and radio VLSI

5. Design of mixed-signal VLSI

6. Methods of structural synthesis of analog, digital and mixed VLSI and complex functional blocks

7. Specialized (resistant to special effects, photosensitivity, etc.) VLSI

Simulation

1. Methods of simulation of digital, analog and mixed circuits and systems

2. Methods for radio VLSI simulation

3. Structural, logical, circuit, mixed and layout simulation

4. Methods for generating models and macromodels for VLSI CAD

5. Device and Technology simulation

6. Behavioral simulation

Information processing methods

1. Information coding

2. Digital data processing

3. Use of artificial intelligence methods, neural networks, etc. in micro- and nanoelectronic system designs

4. Unconventional arithmetic

5. High-performance computers

The development of nanoelectronic systems on new principles

1. Nanomagnetic storage devices

2. Magnetosensor structures

Call for participation in the conference program

I stage - After registration at least one of the co-authors of the report one can send an article. To do this, using their registration data, please log in (see upper right corner of screen). Fill in all required fields. On the website you should send a file containing the main text of the article (in Russian or English) and an extended abstract in English (if the main text is in Russian) or a simple abstract in Russian (if the main text of the article in English). Requirements for the articles sent to MES.

II stage - sending additional documents only for the articles, which have been reviewed and accepted to the conference program.

Visit the 10th MES-2021 conference website at: http://www.mes-conference.ru/index.php

[paper] 1.5-nm Node SGT SRAM Cell

[paper] 1.5-nm Node Surrounding Gate Transistor (SGT)-SRAM Cell with Staggered Pillar and Self-Aligned Process for Gate, Bottom Contact, and Pillar“ will be presented by Yisuo Li at virtual IMW on May 21st, 10:20am // Global TCAD Solutions https://t.co/cr2rvkpXij #semi pic.twitter.com/TSXSO5Db6l

— Wladek Grabinski (@wladek60) May 7, 2021

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May 07, 2021 at 11:52AM
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[Workshop] The Future of Nanoelectronics Devices and Systems Beyond Moore

“The Future of Nanoelectronics Devices and Systems Beyond Moore” 

Workshop on August 31, 2021

This one-day Workshop, supported; IEEE, will be devoted to the update of the European contribution to the IRDS Roadmap in the field of More than Moore, Beyond CMOS and Emerging Materials. The main challenges, most promising technologies, needed research efforts and possible applications will be presented in the following sessions; renown EU experts:

• Beyond CMOS and Emerging Materials
• Trends in Beyond CMOS
  Clivia Sotomayor-Torres; ICN2 and Jouni Ahopelto; VTT
• 2D semi-metal to semiconductor transition devices and/or doping of 2D materials
  Farzan Gity; Tyndall
• GeSn/Ge vertical nanowire GAA FETs
  Qing-Tai Zhao; FZJ
• Flexible electronics with 2D materials
  Zhenxing Wang; AMO
• Presentation of the new IRDS More than Moore Roadmap
  Mart Graef; TU Delft
• Energy Harvesting for Autonomous Systems
• Summary of the IRDS Energy Harvesting for Autonomous Systems White Paper
  Gustavo Ardila; UGA
• Energy sustainability problems of IoT networks
  Thomas Skotnicki; CEZAMAT
• Contribution of triboelectricity for kinetic energy harvesting using electrostatic transduction
  Philippe BASSET; ESIEE, Paris
• Smart Sensors
• Summary of the IRDS Smart Sensors White Paper
  Alan O’Riordan; Tyndall
• Sensing at the Edge: Challenges and Opportunities
  Adrian Ionescu; EPFL
• Smart Sensors and Systems for environment and human exposure monitoring
  Carmen Moldovan; IMT
• Smart Energy
• Summary of the IRDS Smart Energy White Paper
  Mikael Ostling; KTH
• Smart power devices based Wide Bandgap semiconductors
  William Vandendaele; CEA LETI
• Materials and substrates for future power devices
  Joff Derluyn; Soitec BU EpiGaN
• Flexible/Wearable Electronics
• Roadmap of Flexible Electronics: Challenges and Possible Solutions; Summary of the IRDS White Paper
  Benjamin Iñiguez; URV
• Schottky barrier and organic devices for neuromorphic circuits
  Laurie Calvet; CNRS; Université Paris Saclay
• New strategies for sustainable electronics
  Elvira Fortunato; UNL

Program: will be available soon

Location information

Registration: free of charge but mandatory; More information: 

contact@sinano.eu and https://eurosoiulis2021.sciencesconf.org/

[C4P] 3rd ACM/IEEE Workshop on Machine Learning for CAD

Call for Papers: MLCAD

 3rd ACM/IEEE Workshop on Machine Learning for CAD
31 August - 2 September 2021  |  Hybrid Workshop

This workshop focuses on Machine Learning (ML) methods for all aspects of CAD and electronic system design. The workshop is sponsored by both the ACM Special Interest Group on Design Automation (SIGDA) and the IEEE Council on Electronic Design Automation (CEDA). The workshop program will, in addition to technical presentations, also have keynotes and invited speakers from major CAD and industrial companies who will present their vision on machine learning for CAD. We encourage senior researchers as well as Ph.D. students to be part of this workshop. Submitted papers which have been accepted for presentation at the workshop will be included in the workshop proceedings. A Best Paper Award will be presented at the workshop. The MLCAD 2021 organizing committee invites proposals for special sessions. A special session is expected to have a minimum of three, up to six speakers, including the organizers, who provide an overview of the topic area. Prospective organizers of special sessions should submit proposals to the special session chair indicating: title and abstract of the session, organizers, a list of topics (please provide a list of all talks, speakers and their short biographies, co-authors, the contact information of the corresponding author, and an abstract of each contribution). Paper submissions are due 16 May 2021. Fo more details on paper submission, visit the website.

Call for Papers

2020 #semi market #hit $473bn https://t.co/6oyRh2ZDhF https://t.co/834LP2CxgJ

2020 #semi market #hit $473bn https://t.co/6oyRh2ZDhF pic.twitter.com/834LP2CxgJ

— Wladek Grabinski (@wladek60) May 6, 2021

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Speed Up SPICE with a GPU

Speed Up SPICE with a GPU

by Daniel Payne 

Circuit designers know that SPICE circuit simulators use a large matrix to simultaneously solve for currents and voltages, taking small enough time steps to ensure convergence and simulation stability. The trouble is that using a general purpose CPU to make these matrix calculations is quite time consuming, meaning that an engineer can wait hours or days to see any simulation results. Since necessity is the mother of all invention, some clever EDA engineers have looked to speed up SPICE circuit simulations by using GPUs.

1.) 

2.) TinySPICE

3.)with CUSPICE

4.) CUDA Circuit Simulator

5.)

6.) 

SPICE Summary

The need to simulate IC designs in a reasonable amount of time at the transistor level has become a real bottleneck for standard cell, memory design and AMS IP design. Designing with FinFET and small geometry nodes only increases the amount of process corners that need to be simulated for a robust design, so speeding up SPICE simulations is quite welcomed. It looks like using a GPU to speed things up is gaining traction in both the commercial and academic segments, and Daniel Payne loves to hear how Synopsys does against the underdog Empyrean [read more...]

IEEE Milestone - ST Multiple Silicon Technologies

IEEE Milestone - ST Multiple Silicon Technologies on a Chip [STM https://t.co/PxSlaIpHmH] #semi pic.twitter.com/Pz0kEyZq6V

— Wladek Grabinski (@wladek60) May 5, 2021

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#Top10 (less 5) Capacity Leaders

#Top10 (less 5) Capacity Leaders

[Mannerisms] https://t.co/ksXc3URuZU#semi pic.twitter.com/BvDzFDtFL1

— Wladek Grabinski (@wladek60) May 5, 2021

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May 05, 2021 at 10:53AM
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We Could Really Have a #Wireless #Power Grid That Runs on #5G

We Could Really Have a #Wireless #Power Grid That Runs on #5G https://t.co/13ndWwPnBK #semi pic.twitter.com/ouljqCRVB0

— Wladek Grabinski (@wladek60) May 5, 2021

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May 05, 2021 at 09:07AM
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[paper] Random Telegraph Noise in Metal‐Oxide Memristors

[paper] Li, X., Zanotti, T., Wang, T., Zhu, K., Puglisi, F. M., Lanza, M., Random Telegraph Noise in Metal‐Oxide Memristors for True Random Number Generators: A Materials Study. Adv. Funct. Mater. 2021, 2102172. https://t.co/VuSUNNZbm4 https://t.co/xxa3wRpRSp#semi pic.twitter.com/8CSdM5cmYk

— Wladek Grabinski (@wladek60) May 4, 2021

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May 04, 2021 at 02:37PM
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[Si2 CMC] to Standardize SPICE Model for SiC MOSFET

May 03, 2021 // By Peter Clarke [eenewsanalog.com] 

The Compact Model Coalition (CMC) working group of the Silicon Integration Initiative (SI2) has agreed to standardize a model for the behaviour of a silicon-carbide MOSFET.

Silicon-carbide offers higher efficiency and faster operation than silicon and has been adopted for several power applications including photovoltaic inverters and converters, industrial motor drives, electric vehicle powertrain and EV charging, and power supply and distribution. A CMC working group will oversee the model development with Analog Devices, Cadence Design Systems, Infineon, Qualcomm, Siemens EDA, Silvaco and Synopsys set to participate.

"I'd encourage companies with a stake in silicon-carbide devices to join this effort and help guide selection of the model which best represents their intended use," 

advised Peter Lee, chair of the CMC.

Now in its 25th year, the Si2 Compact Model Coalition provides semiconductor manufacturers, designers, and simulation tool providers a means to pool resources to fund standardization and optimization of standard compact SPICE models and standard interfaces to promote simulation tool interoperability [Read more...]

[paper] FET Library for VLSI

Taehak Kim¹, Jaehoon Jeong², Seungmin Woo², Jeonggyu Yang¹, Hyunwoo Kim² Ahyeon Nam², Changdong Lee², Jinmin Seo², Minji Kim², Siwon Ryu², Yoonju Oh², and Taigon Song¹,²  

NS3K : A 3nm Nanosheet FET Library for VLSI Prediction in Advanced Nodes 

IEEE ISCAS, 2021, pp. 1-5, DOI 10.1109/ISCAS51556.2021.9401055.

¹School of Electronics Engineering, Kyungpook National University (KNU), Daegu 41566, South Korea
²School of Electronic and Electrical Engineering, Kyungpook National University (KNU), Daegu 41566, South Korea

Abstract: Nanosheet FETs (NSFETs) are expected as future devices that replace FinFETs beyond the 5nm node. Despite the importance of the devices, few studies report the impact of NSFETs in the full-chip level. Therefore, this paper presents NS3K, the first 3nm NSFET library, and presents the results in a full-chip scale. Based on our results, 3nm NSFET reduces power by -27.4%, total wirelength by -25.8%, number of cells by -8.5%, and area by -47.6% over 5nm FinFET, respectively, due to better devices and interconnect scaling. However, careful device/layout designs followed by routing-resource considering standard cells are required to maximize the advantages of 3nm technology. 

Fig: Projected 3nm NSFET library development flow. Upper side of each step shows the names of required tools. Each colored-boxes correspond to the steps required for specific tasks: The blue boxes - device development, the orange boxes - digital design, and the green boxes - back end design, respectively.

Acknowledgements: This research was supported by National R&D Program through the National Research Foundation of Korea (NRF) funded by Ministry of Science and ICT (2020M3H2A1078045). The EDA tool was supported by the IC Design Education Center(IDEC), Korea. This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No.2019R1G1A109470212).

[paper] Compact modeling of lab-on-chip

Alexi Bonament, Morgan Madec and Christophe Lallement

Compact modeling of reaction-diffusion-advection mechanisms 

for the virtual prototyping of lab-on-chip 

2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, pp. 1-5,

doi: 10.1109/ISCAS51556.2021.9401396.

*Laboratory of Engineer Sciences, Computer Science and Imagine (ICube), UMR 7357 (Université de Strasbourg / Centre National de Recherche Scientifique), Strasbourg

Abstract: The topic of this paper is the development of compact models reaction-advection-diffusion phenomenon compatible with a SPICE simulation environment. From a mathematical perspective, biological systems that involve such phenomena are described by partial differential equations, which are not naturally handeled by SPICE. Our approach consists of discretizing these equations according to the finite-difference method and converting the resulting set of ordinary differential equations into an assembly of elementary equivalent electronic circuits written in Verilog-A. The main interest of this approach is the capability of coupling such models with third-party SPICE models of electronic circuits, sensors and transducers as well as biochemical models that can also be written in SPICE. The tool is validated both on simple problems for which analytical solutions are known and by comparison with a finite element simulator of reference

Fig: Core modules of the designed tool. Labels indicate the programming language.

Acknowledgment: This research was supported by the European Regional Development Fund (ERDF) and the Interreg V Upper Rhine Offensive Sciences Program (Project 3.14 – Water Pollution Sensor).

[paper] Dynamic Simulation of a-IGZO TFT Circuits Using AFCM

Y. Hernández-Barrios¹, J. N. Gaspar-Angeles¹, M. Estrada¹, B. Íñiguez², And A. Cerdeira¹

Dynamic Simulation of a-IGZO TFT Circuits Using the Analytical Full Capacitance Model (AFCM)

IEEE Journal of the Electron Devices Society, vol. 9, pp. 464-468, 2021, 

doi: 10.1109/JEDS.2020.3045347

1 SEES, Departamento de Ingeniería Eléctrica, CINVESTAV-IPN, Mexico City 07360, Mexico
2 Departament d’Enginyeria Electrònica, Elèctrica i Automàtica, URV, Tarragona 43007, Spain

Abstract: The Analytical Full Capacitance Model (AFCM) for amorphous oxide semiconductors thin film transistors (AOSTFTs) is first validated, using a 19-stages Ring Oscillator (RO) fabricated and measured. The model was described in Verilog-A language to use it in a circuit simulator in this case SmartSpice from Silvaco. The model includes the extrinsic effects related to specific overlap capacitances present in bottom-gate AOSTFT structures. The dynamic behavior of the simulated circuit, when the TFT internal capacitances are increased or decreased and for different supply voltages of 10, 15 and 20 V, is compared with measured characteristics, obtaining a very good agreement. Afterwards, the AFCM is used to simulate the dynamic behavior of a pixel control circuit for a light emitting diode active matrix display (AMOLED), using an AOSTFT.

FIG: Fabricated and measured 19-stages Ring Oscillator (RO)

of amorphous oxide semiconductors (AOS) thin film transistors (TFTs) 

Aknowlwgement: This work was supported in part by the Consejo Nacional de Ciencia y Tecnología (CONACYT) under Project 237213 and Project 236887; in part by the H2020 program of the European Union under Contract 645760 (DOMINO); in part by contract “Thin Oxide TFT SPICE Model” with Silvaco Inc., under Grant T12129S; and in part by ICREA Academia 2013 from ICREA Institute and the Spanish Ministry of Economy and Competitiveness under Project TEC2015-67883-R GREENSENSE.

 

[paper] Does the Threshold Voltage Extraction Method Affect Device Variability?

Gabriel Espiñeira; Antonio J. García-Loureiro; Natalia Seoane

Does the Threshold Voltage Extraction Method Affect Device Variability?

IEEE J-EDS, vol. 9, pp. 469-475, 2021,

DOI 10.1109/JEDS.2020.3046122.

* CITIUS, Universidade de Santiago de Compostela, Galicia, Spain

Abstract: The gate-all-around nanowire FET (GAA NW FET) is one of the most promising architectures for the next generation of transistors as it provides better performance than current mass-produced FinFETs, but it has been proven to be strongly affected by variability. For this reason, it is essential to be able to characterize device performance which is done by extracting the figures of merit (FoM) using data from the IV curve. In this work, we use numerical simulations to evaluate the effect of the threshold voltage ( VTH ) extraction method on the variability estimation for a gate-all-around nanowire FET. For that, we analyse the impact of four sources of variability: gate edge roughness (GER), line edge roughness (LER), metal grain granularity (MGG) and random discrete dopants (RDD). We have considered five different extraction methods: the second derivative (SD), constant current (CC), linear extrapolation (LE), third derivative (TD) and transconductance-to-current-ratio (TCR). For the ideal non-deformed device at high drain bias, the effect of the extraction technique can lead to a 137 mV difference in VTH and an 89 mV/V difference in the drain-induced-barrier-lowering (DIBL), and when considering GER and LER variability, the influence of the extraction method leads to differences in the standard deviation values of the VTH distribution ( σVTH ) of up to 2.3 and 3.7 mV respectively, values comparable to intrinsic parameter variations. Therefore, the VTH extraction technique presents itself as an additional parameter that should be included in performance comparisons as it can heavily impact the results.

FIG: General capabilities of the FoMPy library [1]. FoMPy is able to import your data into a dataset, and after optional conditioning (data filtering or interpolation) is able to extract and plot some of the most commonly studied FoMs.

This work was supported in part by the Spanish Government under Grant PID2019-104834GB-100 and Grant RYC-2017-23312, and in part by the Xunta de Galicia and FEDER (accreditation 2016–2019) under Grant GRC 2014/008, Grant ED431G/08, and Grant ED431F-2020/008.

REF:

[1] FoMpy: A figure of merit extraction tool for semiconductor device simulations <https://github.com/gabrielesp/FoMpy>

[2] VENDES. A.J.Garcia-Loureiro, N.Seoane, M.Aldegunde, R.Valin, A.Asenov, A.Martinez and K.Kalna “Implementation of the Density Gradient Quantum Corrections for 3-D Simulations of Multigate Nanoscaled Transistors”, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst, June 2011 doi=10.1109/TCAD.2011.2107990

[3] G.Espiñeira, N.Seoane, D.Nagy, G.Indalecio and A.J.García Loureiro, “FoMPy: A figure of merit extraction tool for semiconductor device simulations” in 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) doi:10.1109/ULIS.2018.8354752

[4] G.Espiñeira, D.Nagy, G.Indalecio, A.J.García Loureiro and N.Seoane, “Impact of threshold voltage extraction methods on semiconductor device variability” Solid-State Electronics, Volume 159, 2019, Pages 165-170, https://doi.org/10.1016/j.sse.2019.03.055

[PhD] VLSI Interconnect Reliability

Shaoyi Peng

Modeling and Simulation Methods for VLSI Interconnect Reliability Focusing 

on Time Dependent Dielectric Breakdown

PhD Dissertation in Electrical Engineering

University of California Riverside

https://escholarship.org/uc/item/966241xk (March 2021)

Abstract: Time dependent dielectric breakdown (TDDB) is one of the important failure mechanisms for Copper (Cu) interconnects that are used in VLSI circuits. This reliability effect becomes more severe as the space between wires is shrinking and low-k dielectric materials (low electrical and mechanical strength) are used. There are many studies and theories focusing on the physics of it. However, there is limited research from the electronics design automation (EDA) perspective on this topic, aiming to evaluate, or alleviate it from the perspective of designing a VLSI chip. This thesis compiles several studies into evaluating TDDB on the circuit level, and engineering methods that help the evaluation. The first work extends the study of a published physics model on simplified yet practical cases. It simplifies the calculation of lifetime by deriving an analytic solution and applying fitting methods. The second study proposes a new way to evaluate lifetime of a chip by extending the models of simple interconnect structures to the complete chip. This method is more robust as it focuses more on a complete chip. However, heavy dependence of finite element method (FEM) makes the flow very slow. The third study adopts machine learning methods to accelerate this slow evaluation process. The proposed method is also applicable to other similar electrostatics applications. Last but not least, the fourth study focuses on a GPU based LU factorization algorithm, which, on a broader aspect, is a universal numerical algorithm used in many different simulation applications, which can be helpful to TDDB evaluations as it can be used in FEM.

Fig: Structure of two copper interconnect wires and the IMD in the cross-section SEM image after TDDB failure [sem]

REF: 

[sem] N. Suzumura, S. Yamamoto, D. Kodama, K. Makabe, J. Komori, E. Murakami, S. Maegawa, and K Kubota. A new TDDB degradation model based on Cu ion drift in Cu interconnect dielectrics. In IEEE Int. Reliability Physics Symposium (IRPS), pages 26–30, 2006.

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[paper] Physical parameter-based data-driven modeling

Gokhan Satilmis¹, Filiz Gunes², Peyman Mahouti³

Physical parameter-based data-driven modeling of small signal parameters of a metal-semiconductor field-effect transistor

International Journal of Numerical Modelling: Electronic Networks, Devices and Fields 

(IJNM 2020): e2840

1 Department of Electric and Electronic Engineering, Mus¸ Alparslan University, Mus, Turkey
2 Department of Electronics and Communication Engineering, Yıldız Technical University, Istanbul, Turkey
3 Department of Electronic and Automation, Vocational School of Technical Sciences, Istanbul University Cerrahpasa, Istanbul, Turkey

Abstract: In this work, physical parameter-based modeling of small signal parameters for a metal-semiconductor field-effect transistor (MESFET) has been carried out as continuous functions of drain voltage, gate voltage, frequency, and gate width. For this purpose, a device simulator has been used to generate a big dataset of which the physical device parameters included material type, doping concentration and profile, contact type, gate length, gate width, and work function. Five state-of-the-art algorithms: multi-layer perceptron (MLP), IBk, K*, Bagging, and REPTree have been used for creating a regression model. The symbolic regression algorithm has been used to obtain analytical expressions of the real and imaginary parts of the Scattering (S) parameters using the physics-based generated dataset. The regression performances of all the benchmarks and the symbolic regression have been compared to references from the device simulator results. The results of the derived equations and the best algorithms have been then compared to the device simulator results, with case studies for validation. The DC performance characteristics of the MESFET have been also obtained. The proposed model can be used to predict the small signal parameters of new devices prior to development, and allows for both the device and circuit to be optimized for specific applications.

Fig: Input and output parameters used for the MESFET simulations

Acknowledgements: We would like to express our special appreciation and gratitude to the DataRobot Company for providing the software license

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[papers] Compact Modeling

[1] Nicolo Zagni; Simulation and Modeling Methods for Predicting Performance and Reliability Limits of 21st-Century Electronics; PhD Thesis, Universita Degli Estudi Di Modena e Reggio Emilia; Anno Accademico 2019–2020 (CICLO XXXIII)

Abstract: In recent years, a plethora of novel semiconductor devices have started emerging as worthy heirs of Silicon-based transistors – giving rise to the ’post-Moore’ era. Traditional electronics is mostly based on Si devices, – from logic to memory, to high frequency/power and sensing applications – but this paradigm is changing thanks to the developments in different fields ranging from physics and semiconductor materials, to processing techniques and computing architectures. In this hectic new scenario, before even considering a new technology as a replacement of the existing ones, the limiting factors to its performance and reliability need to be well-understood and engineered for. In this sense, simulations and physics-based modeling represent critical tools to make sure that newly conceived technologies stand up to the requirements of 21st century electronics. In this thesis, state-of-the-art simulation and compact modeling tools are exploited to analyze the performance and reliability limits of several emerging technologies. Specifically, this dissertation is focused on four application scenarios and the relative candidate technologies that aim to providing enhanced performance/reliability compared to Si-based counterparts. These are: i) III-V MOSFETs for logic/digital circuits, ii) resistive-RAMs and ferroelectric-FETs for non-volatile memory and in-memory computing, iii) GaN-based high-speed transistors for power applications, and iv) negative capacitance transistors for biosensing.

Fig: Energy bandgap (Eg) vs lattice constant (a) of different semiconductor materials, showing that In0.57Ga0.43As has the same lattice constant as InP. Adapted from: https://www.iue.tuwien.ac.at/phd/brech/diss.htm (visited on 12/20/2020).

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[2] G. Maroli, A. Fontana, S. M. Pazos, F. Palumbo and P. Julián, "A Geometric Modeling Approach for Flexible, Printed Square Planar Inductors under Stretch," 2021 Argentine Conference on Electronics (CAE), Bahia Blanca, Argentina, 2021, pp. 61-66, DOI: 10.1109/CAE51562.2021.9397568.

Abstract: In this work a compact model for square planar inductors printed on flexible substrate is proposed. The approach considers the deformation of the metal traces of square spiral inductors when the substrate is subjected to physical stretch. The model considers a typical pi-network for the device, where each component is calculated for different stretching values adapting widely accepted models on the literature for the total inductance, the AC resistance and the ground coupling and inter-wounding capacitances. Model results are contrasted to 3D full electromagnetic wave simulations under parametric sweeps of the dimensions calculated under stretch. Results show good agreement within a 20 % stretch up to the first resonance frequency of the structure. The model can prove useful for the optimization of component design for printed applications on flexible substrates.

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[3] H. Kikuchihara et al., "Modeling of SJ-MOSFET for High-Voltage Applications with Inclusion of Carrier Dynamics during Switching," 2021 International Symposium on Devices, Circuits and Systems (ISDCS), Higashihiroshima, Japan, 2021, pp. 1-4, DOI: 10.1109/ISDCS52006.2021.9397904.

Abstract: Demands for higher-voltage MOSFET application are increasing, for which a Super-Junction MOSFET, sustaining the voltages in the range of 500V, has been developed based on the trench-type structure. Due to the huge bias applied, a new leakage-current type is induced during switching, which causes a switching-power-loss increase. Creating a compact model for circuit design, which includes this additional leakage current, is the purpose of the present development. The model describes the depletion-width variation, caused during the switching-on of the device, with the use of the internal node potential, determined accurately by iteration. It is verified, that the new compact model can accurately predict the device performances for different device structures. This capability can be used for device optimization to realize low-power circuitry.

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[paper] Deep-Learning Assisted Compact Modeling

Hei Kam

Deep-Learning Assisted Compact Modeling of Nanoscale Transistor

CS230 Deep Learning; Stanford University (2021)

Abstract - Transistors are the basic building blocks for all electronics. Accurate prediction of their current-voltage (IV) characteristics enables circuit simulations before the expensive silicon tape-out. In this work, we propose using deep neural network to improve the accuracy for the conventional, physics-based compact model for nanoscale transistors. Physics-driven requirements on the neural network are discussed. Using finite element simulation as the input dataset, together with a neural network with roughly 30 neurons, the final IV model can well-predict the IV to within 1%. This modelling methodologies can be extended for other transistor properties such as capacitance-voltage (CV) characteristics, and the trained model can readily be implemented by the hardware description language (HDL) such as Verilog-A for circuit simulation. The EKV model [1-2] is used as an example. Other transistor models such as BSIM-MG [3] or PSP [4] model can also be used.

Fig: Architecture for the 3-layer neural network together with the aforementioned transformation T. Hyperbolic tangent function tanh(x) is used as the activation function for the input and hidden layers due to its infinite differentiability.

References:

[1] Enz, Christian C., Eric A. Vittoz; "Charge-based MOS transistor modeling." John Wiely & Sons Inc 68 (2006).

[2] FOSS EKV 2.6 Compact Model <https://github.com/ekv26/model>

[3] Khandelwal, Sourabh, et al. "BSIM-IMG: A compact model for ultrathin-body SOI MOSFETs with back-gate control." IEEE Transactions on Electron Devices 59.8 (2012): 2019-2026.

[4] Gildenblat, G., et al. "PSP Model." Department of Electrical Engineering, The Pennsylvania State University and Philips Research, (Aug. 2005)