[paper] Does the Threshold Voltage Extraction Method Affect Device Variability?

Gabriel Espiñeira; Antonio J. García-Loureiro; Natalia Seoane

Does the Threshold Voltage Extraction Method Affect Device Variability?

IEEE J-EDS, vol. 9, pp. 469-475, 2021,

DOI 10.1109/JEDS.2020.3046122.

* CITIUS, Universidade de Santiago de Compostela, Galicia, Spain

Abstract: The gate-all-around nanowire FET (GAA NW FET) is one of the most promising architectures for the next generation of transistors as it provides better performance than current mass-produced FinFETs, but it has been proven to be strongly affected by variability. For this reason, it is essential to be able to characterize device performance which is done by extracting the figures of merit (FoM) using data from the IV curve. In this work, we use numerical simulations to evaluate the effect of the threshold voltage ( VTH ) extraction method on the variability estimation for a gate-all-around nanowire FET. For that, we analyse the impact of four sources of variability: gate edge roughness (GER), line edge roughness (LER), metal grain granularity (MGG) and random discrete dopants (RDD). We have considered five different extraction methods: the second derivative (SD), constant current (CC), linear extrapolation (LE), third derivative (TD) and transconductance-to-current-ratio (TCR). For the ideal non-deformed device at high drain bias, the effect of the extraction technique can lead to a 137 mV difference in VTH and an 89 mV/V difference in the drain-induced-barrier-lowering (DIBL), and when considering GER and LER variability, the influence of the extraction method leads to differences in the standard deviation values of the VTH distribution ( σVTH ) of up to 2.3 and 3.7 mV respectively, values comparable to intrinsic parameter variations. Therefore, the VTH extraction technique presents itself as an additional parameter that should be included in performance comparisons as it can heavily impact the results.

FIG: General capabilities of the FoMPy library [1]. FoMPy is able to import your data into a dataset, and after optional conditioning (data filtering or interpolation) is able to extract and plot some of the most commonly studied FoMs.

This work was supported in part by the Spanish Government under Grant PID2019-104834GB-100 and Grant RYC-2017-23312, and in part by the Xunta de Galicia and FEDER (accreditation 2016–2019) under Grant GRC 2014/008, Grant ED431G/08, and Grant ED431F-2020/008.

REF:

[1] FoMpy: A figure of merit extraction tool for semiconductor device simulations <https://github.com/gabrielesp/FoMpy>

[2] VENDES. A.J.Garcia-Loureiro, N.Seoane, M.Aldegunde, R.Valin, A.Asenov, A.Martinez and K.Kalna “Implementation of the Density Gradient Quantum Corrections for 3-D Simulations of Multigate Nanoscaled Transistors”, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst, June 2011 doi=10.1109/TCAD.2011.2107990

[3] G.Espiñeira, N.Seoane, D.Nagy, G.Indalecio and A.J.García Loureiro, “FoMPy: A figure of merit extraction tool for semiconductor device simulations” in 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) doi:10.1109/ULIS.2018.8354752

[4] G.Espiñeira, D.Nagy, G.Indalecio, A.J.García Loureiro and N.Seoane, “Impact of threshold voltage extraction methods on semiconductor device variability” Solid-State Electronics, Volume 159, 2019, Pages 165-170, https://doi.org/10.1016/j.sse.2019.03.055