Taehak Kim1, Jaehoon Jeong2, Seungmin Woo2, Jeonggyu Yang1, Hyunwoo Kim2 Ahyeon Nam2, Changdong Lee2, Jinmin Seo2, Minji Kim2, Siwon Ryu2, Yoonju Oh2, and Taigon Song1,2
NS3K : A 3nm Nanosheet FET Library for VLSI Prediction in Advanced Nodes
IEEE ISCAS, 2021, pp. 1-5, DOI 10.1109/ISCAS51556.2021.9401055.
1School of Electronics Engineering, Kyungpook National University (KNU), Daegu 41566, South Korea
2School of Electronic and Electrical Engineering, Kyungpook National University (KNU), Daegu 41566, South Korea
Abstract: Nanosheet FETs (NSFETs) are expected as future devices that replace FinFETs beyond the 5nm node. Despite the importance of the devices, few studies report the impact of NSFETs in the full-chip level. Therefore, this paper presents NS3K, the first 3nm NSFET library, and presents the results in a full-chip scale. Based on our results, 3nm NSFET reduces power by -27.4%, total wirelength by -25.8%, number of cells by -8.5%, and area by -47.6% over 5nm FinFET, respectively, due to better devices and interconnect scaling. However, careful device/layout designs followed by routing-resource considering standard cells are required to maximize the advantages of 3nm technology.
Fig: Projected 3nm NSFET library development flow. Upper side of each step shows the names of required tools. Each colored-boxes correspond to the steps required for specific tasks: The blue boxes - device development, the orange boxes - digital design, and the green boxes - back end design, respectively.
Acknowledgements: This research was supported by National R&D Program through the National Research Foundation of Korea (NRF) funded by Ministry of Science and ICT (2020M3H2A1078045). The EDA tool was supported by the IC Design Education Center(IDEC), Korea. This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No.2019R1G1A109470212).
