[paper] Dynamic Simulation of a-IGZO TFT Circuits Using AFCM

Y. Hernández-Barrios¹, J. N. Gaspar-Angeles¹, M. Estrada¹, B. Íñiguez², And A. Cerdeira¹

Dynamic Simulation of a-IGZO TFT Circuits Using the Analytical Full Capacitance Model (AFCM)

IEEE Journal of the Electron Devices Society, vol. 9, pp. 464-468, 2021, 

doi: 10.1109/JEDS.2020.3045347

1 SEES, Departamento de Ingeniería Eléctrica, CINVESTAV-IPN, Mexico City 07360, Mexico
2 Departament d’Enginyeria Electrònica, Elèctrica i Automàtica, URV, Tarragona 43007, Spain

Abstract: The Analytical Full Capacitance Model (AFCM) for amorphous oxide semiconductors thin film transistors (AOSTFTs) is first validated, using a 19-stages Ring Oscillator (RO) fabricated and measured. The model was described in Verilog-A language to use it in a circuit simulator in this case SmartSpice from Silvaco. The model includes the extrinsic effects related to specific overlap capacitances present in bottom-gate AOSTFT structures. The dynamic behavior of the simulated circuit, when the TFT internal capacitances are increased or decreased and for different supply voltages of 10, 15 and 20 V, is compared with measured characteristics, obtaining a very good agreement. Afterwards, the AFCM is used to simulate the dynamic behavior of a pixel control circuit for a light emitting diode active matrix display (AMOLED), using an AOSTFT.

FIG: Fabricated and measured 19-stages Ring Oscillator (RO)

of amorphous oxide semiconductors (AOS) thin film transistors (TFTs) 

Aknowlwgement: This work was supported in part by the Consejo Nacional de Ciencia y Tecnología (CONACYT) under Project 237213 and Project 236887; in part by the H2020 program of the European Union under Contract 645760 (DOMINO); in part by contract “Thin Oxide TFT SPICE Model” with Silvaco Inc., under Grant T12129S; and in part by ICREA Academia 2013 from ICREA Institute and the Spanish Ministry of Economy and Competitiveness under Project TEC2015-67883-R GREENSENSE.