[paper] Deep-Learning Assisted Compact Modeling

Hei Kam

Deep-Learning Assisted Compact Modeling of Nanoscale Transistor

CS230 Deep Learning; Stanford University (2021)

Abstract - Transistors are the basic building blocks for all electronics. Accurate prediction of their current-voltage (IV) characteristics enables circuit simulations before the expensive silicon tape-out. In this work, we propose using deep neural network to improve the accuracy for the conventional, physics-based compact model for nanoscale transistors. Physics-driven requirements on the neural network are discussed. Using finite element simulation as the input dataset, together with a neural network with roughly 30 neurons, the final IV model can well-predict the IV to within 1%. This modelling methodologies can be extended for other transistor properties such as capacitance-voltage (CV) characteristics, and the trained model can readily be implemented by the hardware description language (HDL) such as Verilog-A for circuit simulation. The EKV model [1-2] is used as an example. Other transistor models such as BSIM-MG [3] or PSP [4] model can also be used.

Fig: Architecture for the 3-layer neural network together with the aforementioned transformation T. Hyperbolic tangent function tanh(x) is used as the activation function for the input and hidden layers due to its infinite differentiability.

References:

[1] Enz, Christian C., Eric A. Vittoz; "Charge-based MOS transistor modeling." John Wiely & Sons Inc 68 (2006).

[2] FOSS EKV 2.6 Compact Model <https://github.com/ekv26/model>

[3] Khandelwal, Sourabh, et al. "BSIM-IMG: A compact model for ultrathin-body SOI MOSFETs with back-gate control." IEEE Transactions on Electron Devices 59.8 (2012): 2019-2026.

[4] Gildenblat, G., et al. "PSP Model." Department of Electrical Engineering, The Pennsylvania State University and Philips Research, (Aug. 2005)