Showing posts with label chip. Show all posts
Showing posts with label chip. Show all posts

Mar 28, 2024

[paper] Chip Placement with Deep Learning

Azalia Mirhoseini, Anna Goldie, Mustafa Yazgan, Joe Jiang, Ebrahim Songhori, Shen Wang, Young-Joon Lee, Eric Johnson, Omkar Pathak, Sungmin Bae Azade, Nazi Jiwoo, Pak Andy, Tong Kavya Srinivasa, William Hang, Emre Tuncer, Anand Babu Quoc, Le James Laudon, Richard Ho, Roger Carpenter, Jeff Dean
Chip placement with deep reinforcement learning
arXiv preprint:2004.10746 (2020)

Abstract: In this work, we present a learning-based approach to chip placement, one of the most complex and time-consuming stages of the chip design process. Unlike prior methods, our approach has the ability to learn from past experience and improve over time. In particular, as we train over a greater number of chip blocks, our method becomes better at rapidly generating optimized placements for previously unseen chip blocks. To achieve these results, we pose placement as a Reinforcement Learning (RL) problem and train an agent to place the nodes of a chip netlist onto a chip canvas. To enable our RL policy to generalize to unseen blocks, we ground representation learning in the supervised task of predicting placement quality. By designing a neural architecture that can accurately predict reward across a wide variety of netlists and their placements, we are able to generate rich feature embeddings of the input netlists. We then use this architecture as the encoder of our policy and value networks to enable transfer learning. Our objective is to minimize PPA (power, performance, and area), and we show that, in under 6 hours, our method can generate placements that are superhuman or comparable on modern accelerator netlists, whereas existing baselines require human experts in the loop and take several weeks.

Fig: Visualization of placements. On the left, zero-shot placements from the pre-trained policy and on the right, placements from the finetuned policy are shown. The zero-shot policy placements are generated at inference time on a previously unseen chip. The pre-trained policy network (with no fine-tuning) places the standard cells in the center of the canvas surrounded by macros, which is already quite close to the optimal arrangement and in line with the intuitions of physical design experts.

Acknowledgments: This project was a collaboration between Google Research and the Google Chip Implementation and Infrastructure (CI2) Team. We would like to thank Cliff Young, Ed Chi, Chip Stratakos, Sudip Roy, Amir Yazdanbakhsh, Nathan Myung-Chul Kim, Sachin Agarwal, Bin Li, Martin Abadi, Amir Salek, Samy Bengio, and David Patterson for their help and support.


Nov 2, 2023

[paper] ChipNeMo

Mingjie Liu, Teo Ene, Robert Kirby, Chris Cheng, Nathaniel Pinckney, Rongjian LiangJonah Alben, Himyanshu Anand, Sanmitra Banerjee, Ismet Bayraktaroglu, Bonita Bhaskaran Bryan Catanzaro, Arjun Chaudhuri, Sharon Clay, Bill Dally, Laura Dang, Parikshit Deshpande Siddhanth Dhodhi, Sameer Halepete, Eric Hill, Jiashang Hu, Sumit Jain, Brucek Khailany Kishor Kunal, Xiaowei Li, Hao Liu, Stuart Oberman, Sujeet Omar, Sreedhar Pratty, Ambar Sarkar Zhengjiang Shao, Hanfei Sun, Pratik P Suthar, Varun Tej, Kaizhe Xu, Haoxing Ren
ChipNeMo: Domain-Adapted LLMs for Chip Design
arXiv:2311.00176 [cs.CL]
DOI: 10.48550/arXiv.2311.00176

* NVIDIA

Abstract: ChipNeMo aims to explore the applications of large language models (LLMs) for industrial chip design. Instead of directly deploying off-the-shelf commercial or open-source LLMs, we instead adopt the following domain adaptation techniques: custom tokenizers, domain-adaptive continued pretraining, supervised fine-tuning (SFT) with domain-specific instructions, and domain-adapted retrieval models. We evaluate these methods on three selected LLM applications for chip design: an engineering assistant chatbot, EDA script generation, and bug summarization and analysis. Our results show that these domain adaptation techniques enable significant LLM performance improvements over general-purpose base models across the three evaluated applications, enabling up to 5x model size reduction with similar or better performance on a range of design tasks. Our findings also indicate that there’s still room for improvement between our current results and ideal outcomes. We believe that further investigation of domain-adapted LLM approaches will help close this gap in the future.
Fig: LLM script generator integration with EDA tools

Acknowledgements: The authors would like to thank: NVIDIA IT teams for their support on NVBugs integration; NVIDIA Hardware Security team for their support on security issues; NVIDIA NeMo teams for their support and guidance on training and inference of ChipNeMo models; NVIDIA Infrastructure teams for supporting the GPU training and inference resources for the project; NVIDIA Hardware design teams for their support and insight.

Feb 3, 2022

[paper] Piezosensitive Pressure Sensor Chip

Mikhail Basov
Pressure sensor chip utilizing electrical circuit of piezosensitive differential amplifier with negative feedback loop (PDA-NFL) for 5 kPa
XI International Scientific and Technical Conference 
"Micro-, and Nanotechnology in Electronics", 
Elbrus, Russia; June 2021
  
Dukhov Automatics Research Institute VNIIA, Moscow

Abstract: High sensitive (S=11.2±1.8 mV/V/kPa with nonlinearity error 2KNL=0.15±0.09 % /FS) small-sized (4.00x4.00 mm2) silicon pressure sensor chip utilizing new electrical circuit for microelectromechanical systems (MEMS) in the form of differential amplifier with negative feedback loop (PDA-NFL) for 5 kPa differential was developed. The advantages are demonstrated in the array of output characteristics, which prove the relevance of the presented development, relative to modern developments of pressure sensors with Wheatstone bridge electrical circuit for 5 kPa range.

Fig: a) Pressure sensor chip, b) its assembled structure




Feb 21, 2017

1-cent "lab on a chip" could save lives

Rahim Esfandyarpour, Stanford University, helped to develop a way to create a diagnostic "lab on a chip" for just a penny:
"I'm pretty sure it will open a window for researchers because it makes life much easier for them - just print it and use it," said Esfandyarpour. The results of this research were recently published in the journal Proceedings of the National Academy of Sciences [Source: Stanford Medicine]