Circuit Design and Simulation Marathon using eSIM

 

Indian Institute of Technology, Bombay

We are happy to announce the first ever #Circuit #Design and #Simulation #Marathon using #eSim! This event is jointly organized by #FOSSEE and VLSI System Design. The FOSSEE project developed at Indian Institute of Technology, Bombay is powered by MINISTRY OF EDUCATION, GOVERNMENT OF INDIA.

To know more about the Circuit Design and Simulation Marathon, please visit https://hackathon.fossee.in/esim/

Important dates:
>> Registration: 21 May 2021 - 15 June 2021
>> Marathon Launch : 17 June 2021

FreePDK15: Process Design kit for 15-nm FinFETs

Development of a Predictive Process Design kit for 15-nm FinFETs: FreePDK15 

Kirti Bhanushali, Chinmay Tembe, and W. Rhett Davis 

arXiv:2009.04600v1 [cs.AR] 9 Sep 2020

Abstract: FinFETs are predicted to advance semiconductor scaling for sub-20nm devices. In order to support their introduction into research and universities it is crucial to develop an open source predictive process design kit. This paper discusses in detail the design process for such a kit for 15nm FinFET devices, called the FreePDK15. The kit consists of a layer stack with thirteen-metal layers based on hierarchical-scaling used in ASIC architecture, Middle-of-Line local interconnect layers and a set of Front-End-of-Line layers. The physical and geometrical properties of these layers are defined and these properties determine the density and parasitics of the design. The design rules are laid down considering additional guidelines for process variability, challenges involved in FinFET fabrication and a unique set of design rules are developed for critical dimensions. Layout extraction including modified rules for determining the geometrical characteristics of FinFET layouts are implemented and discussed to obtain successful Layout Versus Schematic checks for a set of layouts. Moreover, additional parasitic components of a standard FinFET device are analyzed and the parasitic extraction of sample layouts is performed. These extraction results are then compared and assessed against the validation models.

FIG: Middle-of-Line layers used as interconnects

Acknowledgment: The authors would like to thank Paul Franzon at NC State University. The authors would like to thank Mentor Graphics, since this project would not have been possible without their generous gift of supporting funds and Calibre licenses. The authors would also like to thank Tarek Ramadan, Ahmed Hammed Fathy, Omar El-Sewefy, Ahmed El-Kordy, Hend Wagieh and the team at Mentor Graphics for development of the first set of design rules and their constant support.In addition, the authors would like to thank and acknowledge Alexandre Toniolo at Nangate for clarifying the vision of MOL layers. We would also like to thank Cadence designsystems for use of the virtuoso software and Synopsys Inc.for use of Pycell studio. The authors would also like to thanks Vikas Sharma for P-Cells, Vidyanandgouda Patil for design rule fixes and Namrata Sampat for help cleaning up the distribution.