[paper] TCAD modeling of neuromorphic systems based on ferroelectric tunnel junctions

Yu He, Wei-Choon Ng and Lee Smith

TCAD modeling of neuromorphic systems based on ferroelectric tunnel junctions

J Comput Electron (2020)

DOI: 10.1007/s10825-020-01544-z

Abstract: A new compact model for HfO2-based ferroelectric tunnel junction (FTJ) memristors is constructed based on detailed physical modeling using calibrated TCAD simulations. A multi-domain configuration of the ferroelectric material is demonstrated to produce quasi-continuous conductance of the FTJ. This behavior is demonstrated to enable a robust spike-timing-dependent plasticity-type learning capability, making FTJs suitable for use as synaptic memristors in a spiking neural network. Using both TCAD–SPICE mixed-mode and pure SPICE compact model approaches, we apply the newly developed model to a crossbar array configuration in a handwritten digit recognition neuromorphic system and demonstrate an 80% successful recognition rate. The applied methodology demonstrates the use of TCAD to help develop and calibrate SPICE models in the study of neuromorphic systems.

Fig: Electric field–polarization relationship. Solid line: multi-domain simulation; dashed line: single-domain simulation; dot: measurement 

[paper] Atomistic Level Simulation of GaNFET

R. K. Nanda¹, E. Mohapatra¹, T. P. Dash¹, P. Saxena², P. Srivastava², R. Trigutnayat²
and C. K. Maiti¹

Atomistic Level Process to Device Simulation of GaNFET Using TNL TCAD Tools

chapter in Lecture Notes in Electrical Engineering book series (LNEE, volume 665)

doi:10.1007/978-981-15-5262-5 

¹Department of Electronics and Communication Engineering, Siksha ‘O’ Anusandhan, Bhubaneswar, Odisha 751030, India

²Tech Next Lab (P) Limited, Niwaz Ganj, Lucknow 226003, India

Abstract: An atomistic level process to device simulation tools developed by Tech Next Lab (TNL) is reported. Modeling of the deposition of high-quality ultrathin AlGaN epitaxial films grown on GaN substrates by molecular beam epitaxy (MBE) has been performed. The surface morphology, crystalline quality, and interfacial property of as-grown AlGaN epitaxial films on GaN substrates are studied using simulation. The epitaxial layer characterization for extract of exact carrier mobility and use of epitaxially grown material for GaN-FET device application has been demonstrated. Results obtained on the basis of process to device simulation have been calibrated with reported results.

Fig: Device structure with 25 nm thick AlGaN/GaN layer grown on SiC (100) substrate and its output Id –Vd characteristics

Learn more: http://www.technextlab.com/index.html

[paper] Compact Modeling of Parasitic FET capacitance

Sharma, S. M., Singh, A., Dasgupta, S., & Kartikeyan, M. V. 

A review on the compact modeling of parasitic capacitance: 

from basic to advanced FETs. 

Journal of Computational Electronics

DOI: 10.1007/s10825-020-01515-4

Abstract: This paper presents a review on the development of parasitic-capacitance modeling for metal–oxide–semiconductor feldefect transistors (MOSFETs), covering models developed for the simple parallel-plate capacitance and the nonplanar and coplanar plate capacitances required for the intrinsic and extrinsic part of such devices. A comparative study of various extrinsic capacitance models with respect to a reference model is used to analyze the benefts of the various approaches. Capacitance models for basic MOSFETs and advance multigate FETs with two-dimensional (2D) and three-dimensional (3D) structures are reviewed. It is found that the elliptical feld lines between the gate electrodes and source/drain region are modeled very well, while deviations of ±2% in the orthogonal plate capacitance are observed when the gate electrode thickness is varied from 5 to 20nm.

Fig: The 3D structure of a FinFET

Acknowledgements: The authors would like to thank the Department of Electronics and Communication Engineering, IIT Roorkee, for their valuable support in carrying out this research work.

[paper] Organic Permeable Base Transistors

Darbandy, G., Dollinger, F., Formánek, P., Hübner, R., Resch, S., Roemer, C., Fischer, A., Leo, K., Kloes, A., Kleemann, H., 

Unraveling Structure and Device Operation of Organic Permeable Base Transistors

Adv. Electron. Mater. 2020, 2000230 

DOI 10.1002/aelm.202000230

Abstract: Organic permeable base transistors (OPBTs) are of great interest for flexible electronic circuits, as they offer very large on‐current density and a record‐high transition frequency. They rely on a vertical device architecture with current transport through native pinholes in a central base electrode. This study investigates the impact of pinhole density and pinhole diameter on the DC device performance in OPBTs based on experimental data and TCAD simulation results. A pinhole density of N Pin = 54 µm−2 and pinhole diameters around L Pin = 15 nm are found in the devices. Simulations show that a variation of pinhole diameter and density around these numbers has only a minor impact on the DC device characteristics. A variation of the pinhole diameter and density by up to 100% lead to a deviation of less than 4% in threshold voltage, on/off current ratio, and subthreshold slope. Hence, the fabrication of OPBTs with reliable device characteristics is possible regardless of statistical deviations in thin film formation.

Fig.: Device stack of an OPBT. The central base electrode is permeable to electrons. The device current flows between emitter and collector, while the base layer is passivated by an oxide layer.

The device current can be modulated by the base‐emitter voltage V_BE

Acknowledgements: G.D. and F.D. contributed equally to this work. This project was funded by the German Research Foundation (DFG) under the grants KL 1042/9‐2 and LE 747/52‐2 (SPP FFlexCom) and by the European Community’s Seventh Framework Programme under Grant Agreement No. FP7‐267995 (NUDEV). This work was supported in part by the German Research Foundation (DFG) within the Cluster of Excellence Center for Advancing Electronics Dresden (cfaed) and the DFG project HEFOS (Grant No. FI 2449/1‐1). Furthermore, the use of HZDR Ion Beam Center TEM facilities and the funding of TEM Talos by the German Federal Ministry of Education of Research (BMBF; grant No. 03SF0451) in the frame‐work of HEMCP are acknowledged. The authors thank Tobias Günther and Andreas Wendel of IAPP for sample preparation.

[paper] NESS

Nano-electronic Simulation Software (NESS): 

a flexible nano-device simulation platform

Salim Berrada, Hamilton Carrillo-Nunez, Jaehyun Lee, Cristina Medina-Bailon, Tapas Dutta, Oves Badami, Fikru Adamu-Lema, Vasanthan Thirunavukkarasu, Vihar Georgiev and Asen Asenov 

Journal of Computational Electronics (2020)

DOI: 10.1007/s10825-020-01519-0

Abstract: The aim of this paper is to present a flexible and open-source multi-scale simulation software which has been developed by the Device Modelling Group at the University of Glasgow to study the charge transport in contemporary ultra-scaled Nano-CMOS devices. The name of this new simulation environment is Nano-electronic Simulation Software (NESS). Overall NESS is designed to be flexible, easy to use and extendable. Its main two modules are the structure generator and the numerical solvers module. The structure generator creates the geometry of the devices, defines the materials in each region of the simulation domain and includes eventually sources of statistical variability. The charge transport models and corresponding equations are implemented within the numerical solvers module and solved self-consistently with Poisson equation. Currently, NESS contains a drift–diffusion, Kubo–Greenwood, and non-equilibrium Green’s function (NEGF) solvers. The NEGF solver is the most important transport solver in the current version of NESS. Therefore, this paper is primarily focused on the description of the NEGF methodology and theory. It also provides comparison with the rest of the transport solvers implemented in NESS. The NEGF module in NESS can solve transport problems in the ballistic limit or including electron–phonon scattering. It also contains the Flietner model to compute the band-to-band tunneling current in heterostructures with a direct band gap. Both the structure generator and solvers are linked in NESS to supporting modules such as effective mass extractor and materials database. Simulation results are outputted in text or vtk format in order to be easily visualized and analyzed using 2D and 3D plots. The ultimate goal is for NESS to become open-source, flexible and easy to use TCAD simulation environment which can be used by researchers in both academia and industry and will facilitate collaborative software development.

FIG: Flowchart of NESS detailing its modular structure

NESS will be released in the summer of 2020 as an open-source software which makes it very interesting for both academia and industry in helping to address the challenges subsequent to the further down-scaling of CMOS components.

Acknowledgements: This work was supported by the European Union’s Horizon 2020 research and innovation programme under Grant Agreement No. 688101 SUPERAID7. Also, this project has received funding from EPSRC UKRI under Grant Agreements No. EP/S001131/1 (QSEE) and No. EP/P009972/1 (QUANTDEVMOD).

Webinars by IEEE Photonics Society Student Chapter

The IEEE Photonics Society Student Chapter of Mangalam College of Engineering has organized a series of the webinars to take away some useful stuffs during current COVID-19 quarantine. The webinar #5 was on:

FOSS TCAD/EDA Tools for Semiconductor Device Modeling

Dr. Wladyslaw Grabinski  

MOS-AK Association   

[paper] BSIM-HV: High-Voltage MOSFET Model

H. Agarwal , Member, IEEE, C. Gupta , Graduate Student Member, IEEE, R. Goel , Graduate Student Member, IEEE, P. Kushwaha , Member, IEEE, Y.-K. Lin , Graduate Student Member, IEEE, M.-Y. Kao , Graduate Student Member, IEEE, J.-P. Duarte , Graduate Student Member, IEEE, H.-L. Chang , Member, IEEE, Y. S. Chauhan , Senior Member, IEEE, S. Salahuddin, Fellow, IEEE, and C. Hu, Life Fellow, IEEE

BSIM-HV: High-Voltage MOSFET Model Including Quasi-Saturation and Self-Heating Effect

IEEE TED, vol. 66, no. 10, pp. 4258-4263, Oct. 2019

doi: 10.1109/TED.2019.2933611

Abstract - A BSIM-based compact model for a high-voltage MOSFET is presented. The model uses the BSIM-BULK (formerly BSIM6) model at its core, which has been extended to include the overlap capacitance due to the drift region as well as quasi-saturation effect. The model is symmetric and continuous, is validated with the TCAD simulations and experimental 35- and 90V LDMOS and 40V VDMOS transistors, and shows excellent agreement.

FIG: Schematic of the LDMOS. Lightly doped n-region constitutes the drain. Majority of the applied drain voltage drops across this region, which protects the intrinsic transistor region from breakdown.

Manuscript received March 3, 2019; revised May 23, 2019 and July 24, 2019; accepted July 31, 2019. Date of publication August 26, 2019; date of current version September 20, 2019. This work was supported in part by the members of the Berkeley Center for Negative Capacitance Technology and the members of the Berkeley Device Modeling Center. The review of this article was arranged by Editor B. Iñiguez.

[C4P] ESSDERC TRACK3 Compact Modeling

European ESSDERC/ESSCIRC conference will be organized in Grenoble (F) on Sept.14-18, 2020 with its integral TRACK3: Compact Modeling and Process/Device Simulation which is open for submissions, now. You and all your R&D partners are welcome to submit a modeling paper. The paper submission deadline is April 17, 2020

TRACK3: Compact modeling and process/device simulation (including TCAD and advanced simulation techniques and studies)  focuses on following domains among other R&D topics:

• Compact/SPICE modeling of electronic, optical, organic, and hybrid devices and their IC implementation and interconnection. 
• Verilog-A models of the semiconductor devices (including Bio/Med sensors, MEMS, Microwave, RF, HV and Power, emerging technologies and novel devices)
• Compact/SPICE parameter extraction
• Performance evaluation and open source (FOSS) benchmarking/implementation methodologies
• Modeling of interactions between process, device and circuit design, 
• Foundry/Fabless interface strategies
• Numerical TCAD, analytical, statistical modeling and simulation of electronic, optical and hybrid devices, interconnect, isolation and 2D/3D integration
• Aspects of materials, fabrication processes and devices e.g. advanced physical phenomena (quantum mechanical and non-stationary transport phenomena, ballistic transport, ...)
• Optical, mechanical or electro-thermal modeling and simulation
• DfM, ageing, reliability of materials and devices

Please share our TRACK3 C4P with all your academic and industrial R&D partners active in the compact/SPICE modeling, Verilog-A standardization and TCAD/EDA simulations. Of course, your and your research team proactive contribution to our TRACK3 is more than welcome. I do hope that despite of a last minute notice, with your help, we will be able to draw even more attention to the ESSDERC/ESSCIRC Conference and, in particular, our modeling TRACK3

-- ESSDERC TRACK3 TPC

[paper] Charge-based Modeling of Ultra Narrow Cylindrical Nanowire FETs

Charge-based Modeling of Ultra Narrow Cylindrical Nanowire FETs 

Danial Shafizade, Majid Shalchian and Farzan Jazaeri

IEEE TED, Vol. XX, No. XX, 15 March 2020

Abstract: This brief proposes an analytical approach to model the dc electrical behavior of extremely narrow cylindrical junctionless nanowire field-effect transistor (JLNW-FET). The model includes explicit expressions, taking into account the first order perturbation theory for calculating eigenstates and corresponding wave functions obtained by the Schrodinger equation in the cylindrical coordinate. Assessment of the proposed model with technology computer-aided design (TCAD) simulations and measurement results confirms its validity for all regions of operation. This represents an essential step toward the analysis of circuits mainly biosensors based on junctionless nanowire transistors.

MicroTec: Semiconductor Process and Device Simulator

Software Package for 2D Process and Device Simulation

Version 4.0 for Windows

User’s Manual

Publisher: Siborg Systems Inc

Editor: Michael S. Obrecht

MicroTec allows 2D silicon process modeling including implantation, diffusion and oxidation and 2D steady-state semiconductor device simulation like MOSFET, DMOS, JFET, BJT, IGBT, Schottky, photosensitive devices etc. Although MicroTec is significantly simplified compared to widely available commercial simulators, it nevertheless is a very powerful modeling tool for industrial semiconductor process/device design. In many instances MicroTec outperforms existing commercial tools and it is remarkably robust and easy-to-use.

FIG: MicroTec SibGraf GUI windows

Leti Workshop at SISPAD 2019

Leti is pleased to invite you to attend our ‘Advanced Simulations for Emerging Non-Volatile Memory Technologies’ seminar, which is organized as an official satellite event of the 2019 IEEE SISPAD Conference (http://www.sispad2019.org). By the proposed seminar, we will emphasize how simulation and modeling support memory technology developments and device behavior understanding.

This event will held on Tuesday, September 3rd from 5:00 PM to 7:30 PM, Palazzo di Toppo Wassermann, Università degli Studi di Udine, Udine, Italy (i.e. at the SISPAD 2019 conference location).

PROGRAM

• Welcome and Introduction – T. Poiroux
• Innovative non-volatile memory technologies: a revolution for the storage towards a memory that thinks – G. Navarro
• Electro-thermal and material simulations for PCM – O. Cueto
• Multiphase field method for the simulation of the complex phase changes in PCM – R. Bayle
• Invited talk: Self-consistent TCAD simulation of chemical reactions within electronic devices. Application to CBRAM and OxRAM – Silvaco
• Networking cocktail

Registration is free but, due to limited seats, please register just sending an email to thierry.poiroux@cea.fr and sebastien.martinie@cea.fr.

Feel free to share this invite with your colleagues !

An Empirical Model to Enhance the Flexibility of gm/Id Tuning in BSIM-BULK Model

Ravi Goel, Chetan Gupta, Yogesh S. Chauhan

EE Department, Indian Institute of Technology Kanpur, Kanpur, India

Published in: 2018 5th IEEE Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON)

Abstract: Recent enhancement in BSIM-BULK (formerly BSIM6) model is presented in this work. The industry standard models like BSIM4, PSP, BSIM-BULK etc. lack the parameters for tuning of transconductance to channel current ratio (gm/Id). gm/Id is also a critical figure of merit for analog applications. Here, we propose an empirical model to enhance the flexibility of gm/Id tuning behavior. The proposed model provides good fitting for different channel lengths and drain bias.

Paper Sections:
I. Introduction
II. An Empirical Model for gm/Id Tuning
III. Model Implementation
IV. Model Validation with TCAD
V. Conclusion

Source:
DOI: 10.1109/UPCON.2018.8597065

IEEE Cledo Brunetti Award 2018 presented to Prof.Dr. Siegfried Selberherr

One of the founders of modern Technology Computer Aided Design (TCAD), Siegfried Selberherr has provided modeling and software development tools invaluable to the continued miniaturization of semiconductor devices. TCAD involves the use of computer simulation to develop and optimize semiconductor processing technologies. Selberherr developed MINIMOS for two-dimensional predictive simulation of the electrical characteristics of miniaturized devices to understand and control the short-channel effects and doping profiles encountered as device sizes shrink. MINIMOS was later enhanced for three-dimensional simulation to address energy transport and interface physics. He also created the ZOMBIE and PROMIS simulators, which incorporated mesh generation and programming interfaces. Selberherr then developed the Vienna Integrated System for TCAD Applications (VISTA) to combine both process and device simulation tools in a common framework. An IEEE Fellow, Selberherr is a professor with the Institute for Microelectronics at the Technische Universität Wien, Vienna, Austria.

FOSDEM 2019 CAD and Open Hardware Devroom Call for Participation

This is the call for participation in the FOSDEM 2019 devroom on Computer Aided Design (CAD) tools and Open Hardware, to be held on Sunday 3 February 2019 in Brussels, Belgium. We are looking for contributions under the form of talks and tutorials covering the following main topics:

• Printed Circuit Board (PCB) design tools (e.g. KiCad and gEDA)
• Analogue and digital simulators (e.g. ngspice, Qucs, Gnucap, Xyce, GHDL, Icarus and Verilator)
• Any other EDA tools such as high-level tools for digital hardware design (e.g. Migen) and HDL synthesis tools (e.g. Yosys)
• Field solvers such as openEMS
• Mechanical 2D and 3D CAD tools such as LibreCAD, FreeCAD, OpenSCAD and SolveSpace
• Open Hardware projects such as the Teres laptop and the lowRISC SoC
• Inter-project opportunities for collaboration

We hope to provide an opportunity for attendees to bring themselves up to date on the latest FOSS CAD and Open Hardware developments, share knowledge and identify opportunities to collaborate on development tasks. This devroom is an evolution of the EDA devroom we organised in 2015, 2016 and 2017, which enlarged its scope in the CAD and Open

Hardware devroom in 2018.

Please submit your proposals at
https://penta.fosdem.org/submission/FOSDEM19 

before 1 December 2018.

Important dates
8 December 2018: deadline for submission of proposals
15 December 2018: announcement of final schedule
3 February 2019: devroom day

Digital and analog TFET circuits: Design and benchmark

Solid-State Electronics
Volume 146, August 2018, Pages 50–65
Invited Review

S. Strangio^a,b, F. Settino^a,b, P. Palestri^a, M. Lanuzza^b, F. Crupi^b, D. Esseni^a, L. Selmi^a,c

^aDPIA, Università degli Studi di Udine, Via delle Scienze 206, I-33100 Udine, UD, Italy
^bDIMES, Università della Calabria, Via P. Bucci, 41C, I-87036 Arcavacata di Rende (CS), Italy
^cDipartimento di Ingegneria “Enzo Ferrari”, Università degli Studi di Modena e Reggio Emilia, I-41100 Modena, Italy

ARTICLE INFO: The review of this paper was arranged by Prof. S. Cristoloveanu
https://doi.org/10.1016/j.sse.2018.05.003

HIGHLIGHTS:

• We report simulations of basic analog and digital circuit blocks employing tunnel-FETs.
• Template III-V heterojunction tunnel-FETs are benchmarked against silicon FinFETs for the 10 nm node.
• Performance are evaluated down to VDD = 200 mV.
• Tunnel-FETs result advantageous with respect to silicon FinFET for VDD below approximately 400 mV.

ABSTRACT: In this work, we investigate by means of simulations the performance of basic digital, analog, and mixed-signal circuits employing tunnel-FETs (TFETs). The analysis reviews and complements our previous papers on these topics. By considering the same devices for all the analysis, we are able to draw consistent conclusions for a wide variety of circuits. A virtual complementary TFET technology consisting of III-V heterojunction nanowires is considered. Technology Computer Aided Design (TCAD) models are calibrated against the results of advanced full-quantum simulation tools and then used to generate look-up-tables suited for circuit simulations. The virtual complementary TFET technology is benchmarked against predictive technology models (PTM) of complementary silicon FinFETs for the 10nm node over a wide range of supply voltages (VDD) in the sub-threshold voltage domain considering the same footprint between the vertical TFETs and the lateral FinFETs and the same static power. In spite of the asymmetry between p- and n-type transistors, the results show clear advantages of TFET technology over FinFET for VDD lower than 0.4V. Moreover, we highlight how differences in the I-V characteristics of FinFETs and TFETs suggest to adapt the circuit topologies used to implement basic digital and analog blocks with respect to the most common CMOS solutions.

FIG: Sketch of n- and p-type TFET and FinFET device architectures. The red and blue colors indicate the n- and p-doping types, respectively (green: intrinsic semiconductor, transparent-grey: oxide). TFET dimensions are: LG=20nm, nanowire cross section (LS)=7nm, EOT=1nm. FinFET dimensions are: LG=14nm, tfin=8nm, hfin=21nm, EOT=0.88nm. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)

RG: article reached 2,000 reads

Article reached 2,000 reads: Open-source circuit simulation tools for RF compact semiconductor device modelling

ENBIOS-2D Lab

Aldi Hoxha1, Paolo Scarbolo1, Andrea Cossettini2, Federico Pittino3, Luca Selmi4

1. DPIA, Università degli Studi di Udine 2. University of Udine 3. Università di Udine 4

DPIA, Università degli Studi di Udine, Italy

Abstract: ENBIOS-2D Lab is a tool to illustrate and to study simple Ion Sensitive Field Effect Transistor structures in two dimensions. Together with its companion tool ENBIOS-1D Lab, it is meant for use as a teaching tool in support of undergraduate or graduate courses on the basic physics of transduction in ion and particle sensors, and to assist early stage researchers getting familiar with some basic concepts in the field. At the present stage, ENBIOS-2D Lab supports simulation and visualization of DC I-V characteristics, impedance/admittance spectra as well as DC and AC potential/carrier/ion distributions in simple two-dimensional ISFET structures. A broader set of case studies will become available with future releases of the tool. The companion ENBIOS-1D Lab tool offers the possibility to simulate simple Electrolyte/Insulator/Semiconductor systems in one-dimension. The physical system is modelled with the Poisson/Boltzmann (DC) and Poisson/Nernst/Planck - Poisson/Drift/Diffusion (AC small signal) equations coupled to the site-binding charge model equations at the Electrolyte/Insulator interfaces. Dedicated models are implemented for the frequency and salinity dependence of the electrolyte electrical permittivity and the temperature dependence of the ions' mobility (in water solvent). ENBIOS-2D Lab is powered by ENBIOS, (Electronic Nano-BIOsensor Simulator), a general purpose three-dimensional Control Volume Finite Element Method (CVFEM) simulator developed in-house at the University of Udine - Italy. ENBIOS simulates in three dimensions (3D) the DC and AC small signal impedance response to ions and micro/nanoparticles of three-dimensional devices made of semiconductor, insulator and electrolyte materials.

References:

[1] P. Scarbolo, E. Accastelli, F. Pittino, T. Ernst, C. Guiducci, L. Selmi, “Characterization and modelling of differential sensitivity of nanoribbon-based pH-sensors”, Proceedings of the 2015 Transducers - 18th International Conference on Solid-State Sensors, Actuators and Microsystems (TRANSDUCERS), 21-25 June 2015, pp. 2188-2191

[2] Paolo Scarbolo, Enrico Accastelli, Thomas Ernst, Carlotta Guiducci and Luca Selmi, "Analysis of Dielectric Microbead Detection by Impedance Spectroscopy with Nanoribbons", IEEE Nano Conference, August 2016.

[3] Federico Pittino and Luca Selmi, "Use and comparative assessment of the CVFEM method for Poisson–Boltzmann and Poisson–Nernst–Planck three dimensional simulations of impedimetric nano-biosensors operated in the DC and AC small signal regimes", Comput. Methods Appl. Mech. Engrg., v.278, (2014), pp.902–923.

FOSDEM 2018 CAD and Open Hardware Devroom Call for Participation

(Also visible at https://www.ohwr.org/projects/ohr-meta/wiki/FOSDEM2018)

This is the call for participation in the FOSDEM 2018 devroom on Computer Aided Design (CAD) tools and Open Hardware, to be held on Saturday 3 February 2018 in Brussels, Belgium. We are looking for contributions under the form of talks and tutorials covering the following main topics:

• Printed Circuit Board (PCB) design tools (e.g. KiCad and gEDA)
• Analogue and digital simulators (e.g. ngspice, Qucs, Gnucap, Xyce,GHDL, Icarus and Verilator)
• Any other EDA tools such as high-level tools for digital hardware design (e.g. Migen) and HDL synthesis tools (e.g. Yosys)
• Field solvers such as openEMS
• Mechanical 2D and 3D CAD tools such as LibreCAD, FreeCAD, OpenSCAD andSolveSpace
• Open Hardware projects such as the Teres laptop and the lowRISC SoC
• Inter-project opportunities for collaboration

We hope to provide an opportunity for attendees to bring themselves up to date on the latest FOSS CAD and Open Hardware developments, share knowledge and identify opportunities to collaborate on development tasks. This devroom is an evolution of the EDA devroom we organised in 2015, 2016 and 2017.

The submission process: Please submit your proposals at

https://penta.fosdem.org/submission/FOSDEM18 before 1 December 2017.

If you already have a Pentabarf account (for example as a result of having submitted a proposal in the past), make sure you use it to log in and submit your proposal. Do not create a new account if you already have one. Please provide a bit of information about yourself under Person -> Description -> Abstract. When you submit your proposal (creating an "Event" in Pentabarf), make sure you choose the "CAD and Open Hardware Devroom" in the track drop-down menu. Otherwise your proposal might go unnoticed. Fill in at least a title and abstract for the proposed talk and a suggested duration. Bear in mind that a lot of the value in these meetings comes from the discussions, so please be reasonable regarding the duration of the talk.

Important dates

• 1 December 2017: deadline for submission of proposals
• 8 December 2017: announcement of final schedule
• 3 February 2018: devroom day

Recordings: The FOSDEM organisers hope to be able to live-stream and record all the talks. The recordings will be published under the same licence as all FOSDEM content (CC-BY). Only presentations will be recorded, not informal discussions and whatever happens during the lunch break. By agreeing to present at FOSDEM, you automatically give permission to be recorded. The organisers will agree to make exceptions but only for exceptional and well-reasoned cases.

Mailing list: Feel free to subscribe to the mailing list of the CAD and Open Hardware devroom to submit ideas, ask questions and generally discuss about the event:

https://lists.fosdem.org/listinfo/open-hardware-devroom

Spread the word!

[paper] Design Strategies for Ultralow Power 10nm FinFETs

Design Strategies for Ultralow Power 10nm FinFETs

Abhijeet Walkea^a, Garrett Schlenvogtb^b, Santosh Kurineca^a

^aDepartment of Electrical & Microelectronic Engineering, RIT, New York, USA

^bTCAD Application Engineer, Silvaco

Received 12 June 2017, Accepted 19 June 2017, Available online 20 June 2017

Abstract: In this work, new design strategies for 10nm node NMOS bulk FinFET transistors are investigated to meet low power (LP) (20pA/μm< I_OFF <50pA/μm) and ultralow power (ULP) (I_OFF <20pA/μm) requirements using three dimensional (3D) TCAD simulations. The punch-through stop implant, source and drain junction placement and gate workfunction are varied in order to study the impact on the OFF-state current (I_OFF), transconductance (g_m), gate capacitance (C_gg) and intrinsic frequency (f_T). It is shown that the gate length of 20nm for the 10nm node FinFET can meet the requirements of LP transistors and ULP transistors by source-drain extension engineering, punch-through stop doping concentration, and choice of gate workfunction.

[read more https://doi.org/10.1016/j.sse.2017.06.012]

[paper] Impact of technology scaling on analog and RF performance of SOI–TFET

Impact of technology scaling on analog and RF performance of SOI–TFET

P Kumari, S Dash and G P Mishra
Advances in Natural Sciences: Nanoscience and Nanotechnology, Volume 6, Number 4 

Published 9 October 2015

Abstract

This paper presents both the analytical and simulation study of analog and RF performance for single gate semiconductor on insulator tunnel field effect transistor in an extensive manner. Here 2D drain current model has been developed using initial and final tunneling length of band-to-band process. The investigation is further extended to the quantitative and comprehensive analysis of analog parameters such as surface potential, electric field, tunneling path, and transfer characteristics of the device. The impact of scaling of gate oxide thickness and silicon body thickness on the electrostatic and RF performance of the device is discussed. The analytical model results are validated with TCAD Sentaurus device simulation results [read more...]

Citations
[1] Extensive electrostatic investigation of workfunction-modulated SOI tunnel FETs Subhrasmita Panda et al  2016 Journal of Computational Electronics 15 1326
[2] S. Sahoo et al  2016 337
[3] A comprehensive investigation of silicon film thickness (T SI) of nanoscale DG TFET for low power applications Rajeev Ranjan et al  2016 Advances in Natural Sciences: Nanoscience and Nanotechnology 7 03500
[4] A complete analytical potential based solution for a 4H-SiC MOSFET in nanoscale M K Yadav et al  2016 Advances in Natural Sciences: Nanoscience and Nanotechnology 7 025011
[5] S. Dash et al  2015 447