Showing posts with label GaN-FET. Show all posts
Showing posts with label GaN-FET. Show all posts

Jul 2, 2020

[paper] Atomistic Level Simulation of GaNFET

R. K. Nanda1, E. Mohapatra1, T. P. Dash1, P. Saxena2, P. Srivastava2, R. Trigutnayat2
and C. K. Maiti1
Atomistic Level Process to Device Simulation of GaNFET Using TNL TCAD Tools
chapter in Lecture Notes in Electrical Engineering book series (LNEE, volume 665)
doi:10.1007/978-981-15-5262-5 

1Department of Electronics and Communication Engineering, Siksha ‘O’ Anusandhan, Bhubaneswar, Odisha 751030, India
2Tech Next Lab (P) Limited, Niwaz Ganj, Lucknow 226003, India

Abstract: An atomistic level process to device simulation tools developed by Tech Next Lab (TNL) is reported. Modeling of the deposition of high-quality ultrathin AlGaN epitaxial films grown on GaN substrates by molecular beam epitaxy (MBE) has been performed. The surface morphology, crystalline quality, and interfacial property of as-grown AlGaN epitaxial films on GaN substrates are studied using simulation. The epitaxial layer characterization for extract of exact carrier mobility and use of epitaxially grown material for GaN-FET device application has been demonstrated. Results obtained on the basis of process to device simulation have been calibrated with reported results.

Fig: Device structure with 25 nm thick AlGaN/GaN layer grown on SiC (100) substrate and its output Id –Vd characteristics