[IC Design] Single Photon Counting ASIC for Synchrotron Applications

Ultra-Fast Single Photon Counting ASIC for Fast Synchrotron Applications

Dr hab. inż Piotr Kmon

AGH University, Cracow, Poland

European Synchrotron Radiation Facility (ESRF), Grenoble, France

Abstract: The SPHIRD (Small Pixel High Rate photon counting Detector) project is an R&D study to investigate how far the photon counting X-ray hybrid pixel detector technology can go, regarding photon rate and spatial resolution. A goal was to boost by 30 times the count-rate capabilities of existing detectors of similar pixel size. SPHIRD targets that figure by designing fast front end electronics, by including pile-up compensation techniques in the pixel logic, and by implementing smaller pixels. Each pixel contains fast front-end analog electronics (pulse width is only 18ns) with base-line holder (BLH), a set of discriminators (with offset trimming blocks), ripple counters, and digital blocks. The pixel architecture allows also for operation in conventional mode (STDC) and with different pulse pile-up compensation methods (these are voltage and time based methods named VDIS, TDIS, and FPHC respectively).

Fig: Schematic idea of the recording channel and the chip photo with mounted detector

Technology: TSMC 40nm GP; Die Size: 3.2mm x 3.5mm

Acknowledgements: The chip design was realized by P. Grybos, R. Kleczek, P. Otfinowski, and P. Kmon (AGH) while synchrotron experiments were conducted by P. Fajarado, D. Magalhaes and M. Raut.

References
[1] P. Grybos,et.al., “SPHIRD–Single Photon Counting Pixel Readout ASIC With Pulse Pile-Up Compensation Methods”, IEEE IEEE Transactions on Circuits and Systems--II: Express Briefs, vol. 70, no. 9, 2023, p. 3248-3252.
[2] D. Magalhaes et al., Very High Rate X-ray Photon Counting 2D Detectors with Small Pixels: the SPHIRD Project. 2022 IEEE NSS-MIC-RTSD Conference Proceedings.

ISHI-kai January 2024 event

2024年1月イベント「オープンソースPDK団体」勉強会国内外のオ
ープンソースPDKやEDAの状況について、キーマンに語っていただきます

With the recent rise in the semiconductor industry, the movement of open source PDK and EDA in Japan and overseas has become active. Therefore, in this study session, key people will talk about the status of open source PDK and EDA in Japan and overseas.

Schedule

Friday, January 26, 2024, 18:00-21:00 (Reception: 18:30)

Venue (onsite)

Google Shibuya Office
3-21-3 Shibuya, Shibuya-ku, Tokyo
Shibuya Stream Google reception meeting

Online Broadcast: 

Google Meet: https://meet.google.com/ksa-tjaw-ges

Participation Fee

free

Timetable

Time	Speaker	Title	Lecture Outline
Until 18:30	ISHI-kai	reception	The entrance to the facility closes at this time, so if you are participating locally, please come by this time as much as possible.
18:00 ～ 18:30	ISHI-kai	Chat time	-
18:30 ~ 19:15 (Lecture: 30min, Q&A: 15min)	Takeshi Hamamoto Minimal Fab Propulsion Organization Device Engineer	minimal Fab open PDK	1) What is a minimal fab 2) openPDK 3) Design Contest at Semicon 2023
19:15 ~ 20:00 (Lecture: 30min., Q&A: 15min.)	Junichi Okamura IEEE Senior Member	OpenPDK and the World	-
20:00 ~ 20:45 (Lecture: 30min., Q&A: 15min.)	@noritsuna	About the upcoming open source PDK shuttle	(To be released at a later date)
21:00	ISHI-kai	closing

What is ISHI-kai?

The association was named ISHI-kai (Inter-linked Society on Homemade IC Kai). The name was conceived from the Society Community (Association) that handles open (democratized) ISHI = stone = Silicon = semiconductors (ASIC/LSI/IC) and connects various fields.

OpenMPW (Open Multi Project Wafer), which appeared as a forerunner, is a shuttle program created by Google investing in Efabless, and includes the tools necessary for making semiconductors (ASIC/LSI/IC) (EDA/PDK) to ISHI manufacturing in IC fabs). This is exactly the "openness of semiconductors (ASIC/LSI/IC) and EDA/PDK" of the open source movement (democratization of software) that started with GNU!

Therefore, this association was established as a user society community (association) that focuses not only on experts in semiconductors (ASIC/LSI/IC) in the past, but also on those who see the potential of the open source movement of semiconductors (ASIC/LSI/IC) in the future and those who want to create new semiconductors (ASIC/LSI/IC).

We/ISHI-kai will continue to work toward a world where semiconductors (ASIC/LSI/IC) and EDA/PDK can be used by everyone, just as OSs, compilers, libraries, apps, electronic boards, 3D CAD and 3D printers that we/ISHI-kaire only available to experts can now be used by everyone as open source software, open hardware, open modeling, etc.

As for the future activity plan, we/ISHI-kai have a policy of revolutionizing the semiconductor (ASIC/LSI/IC) field by involving people from other fields, and we/ISHI-kai will hold events such as hands-on seminars for ultra-beginners for other fields and in-depth study sessions for experts, form a team to challenge the OpenMPW shuttle and Chipathon from around the world, and Maker we/ISHI-kai would like to participate in events such as Faire, so thank you.

Precautions

As events move online, we/ISHI-kai ask participants to act in accordance with the spirit of the Code of Conduct. If you have any problems, please contact the organizer. If it is judged that there is no improvement in the request even if there is no abuse such as vandalism or malicious intent, we/ISHI-kai may respond on a case-by-case basis. 

https://www.contributor-covenant.org/ja/version/2/0/code_of_conduct/

Acknowledgements

Thanks to the kindness of Google for providing a real/onsite venue.

[Deadline] #TinyTapeout 3

Are you a #teacher and interested in microelectronics?

Visit https://tinytapeout.com/

#TinyTapeout and #SiliWiz are online tools you can use to learn how ASICs are designed, made and how they work. You can even get your designs affordably manufactured!

Matt Venn has some free slots for #TinyTapeout 3 for you and your students - just send him a DM to get started!

Deadline is 24th April! Apply today at https://tinytapeout.com/

[paper] OpenSpike: An OpenRAM SNN Accelerator

Farhad Modaresi¹, Matthew Guthaus², and Jason K. Eshraghian³
OpenSpike: An OpenRAM SNN Accelerator
arXiv:2302.01015v1 [cs.AR] 2 Feb 2023

1) Dept. of Electrical Engineering Allameh Mohaddes Nouri University Nur, Mazandaran, Iran
2) Dept. of Computer Science and Engineering, UC Santa Cruz Santa Cruz, CA, United States
3) Dept. of Electrical and Computer Engineering, UC Santa Cruz Santa Cruz, CA, United States

Abstract: This paper presents a spiking neural network (SNN) accelerator made using fully open-source EDA tools, process design kit (PDK), and memory macros synthesized using Open- RAM. The chip is taped out in the 130 nm SkyWater process and integrates over 1 million synaptic weights, and offers a reprogrammable architecture. It operates at a clock speed of 40 MHz, a supply of 1.8 V, uses a PicoRV32 core for control, and occupies an area of 33.3 mm2. The throughput of the accelerator is 48,262 images per second with a wallclock time of 20.72 μs, at 56.8 GOPS/W. The spiking neurons use hysteresis to provide an adaptive threshold (i.e., a Schmitt trigger) which can reduce state instability. This results in high performing SNNs across a range of benchmarks that remain competitive with state-of-the-art, full precision SNNs.

The design is open sourced and available online: https://github.com/sfmth/OpenSpike

Fig: OpenSpike core - system architecture and data flow