Showing posts with label Japan. Show all posts
Showing posts with label Japan. Show all posts

Jan 6, 2025

SSCS PICO Chronicle

Mirjana Videnovic-Misic, Harald Pretl, Ali Sabir, Zonghao (Chris) Li, 
and Sadayuki Yoshitomi
SSCS PICO Chronicles: news from the open source community
Date of current version: 14 November 2023
DOI: 10.1109/MSSC.2023.3315888

The Growing Activity of Open Source Chip Design in Japan

The Chipathon 2023 Team Japan consists of 12 volunteers from industry and academia. Since the team members are located in different parts of Japan, the team will be working remotely to design the project. On 4 August, they held a kickoff meeting where the members, who had been working together on Slack, gathered for the first time in person. Although many of the team members have no tape-out experience, they are all truly interested in IC design. The leader of Team Japan is Prof. Akira Tsuchiya at the University of Shiga in Japan (FIG).

Prof. Tsuchiya has been working on open source IC design and has been a volunteer member of the SSCS Chipathon since October 2022. He has promoted open source IC design and SSCS PICO activities in Japan. He held several hands-on events, for example, at the summer camp of the IE- ICE ICD in 2022. Also, he gave several talks about open source IC design and his research on analog synthesis in domestic conferences. And now, he has recruited members and applied to the latest Chipathon. Let’s look forward to the activities of the new members of “Team Japan.”

FIG: Prof. Akira Tsuchiya, an associate professor of the University of Shiga prefecture, 
Japan, and a snapshot of the kickoff meeting (hybrid) of the Chipathon 2023 Japan team





Dec 4, 2013

SISPAD 2014 1st Call for Papers


2014 International Conference on Simulation of Semiconductor Processes and Devices
September 9-11, 2014
Workshop, September 8
Mielparque Yokohama, Yokohama, Japan


The call for papers is also available on SISPAD2014 Web site. Deadline for submission of SISPAD abstracts: March 31, 2014


Any inquiries on submission should be sent to:
  • Steering Chair:  Shinji Odanaka  (Osaka Univ)
  • Conference Chair:  Nobuya Mori  (Osaka Univ)
  • Program Chair:  Kenichiro Sonoda  (Renesas)
  • Program Co-Chair:  Shigeyasu Uno  (Ritsumeikan Univ)

Oct 22, 2013

SISPAD Abstract Submission

2014 International Conference on Simulation of Semiconductor Processes and Devices
September 9 – 11, 2014
Workshop, September 8
Mielparque Yokohama, Yokohama, Japan

Deadline for submission of SISPAD abstract: March 1, 2014

Any inquiries on submission should be sent to:
  • Program Chair:  Ken’ichiro Sonoda (Renesas)
  • Program Co-Chair:  Shigeyasu Uno (Ritsumeikan Univ)

Jan 9, 2013

10th IWCM Workshop Program

10th International Workshop on Compact Modeling 

January 22 (Tue), 2013 

Pacifico Yokohama, Room 419

Yokohama, Japan

Time
#
Title
Authors
Affiliation
9:00-9:10

Opening: H. J.  Mattausch (Workshop Chair)




Power Devices   Chair: D. Navarro


9:10-9:30
1
HiSIM_HV Temperature Modeling for Multi-Geometry LDMOS: Comparison of the Temperature Flag Options
Y. Iino
Silvaco Japan
9:30-9:50
2
Analysis and Further Improvements of the Drain-Resistance Modeling in HiSIM_HV
T. Umeda et al.
Hiroshima University
9:50-10:10
3
Floating-Base Effect Modeling for IGBT Structure using Potential Modification
T. Yamamoto
et al.
Denso
10:10-10:30

- Break -




Novel FET Structures Chair: T. Nakagawa


10:30-10:50
4
Study on Dynamic Threshold Nanowire Tunnel FET
A. Zhang et al.
Peking University
Shenzhen
10:50-11:10
5
A DC Model of TFETs for SPICE Simulations
L. Zhang and M. Chan
HK UST 
11:10-11:30
6
A Surface Potential Based Compact Model of Organic Thin-Film Transistor for Circuit Simulation
T.K. Maiti et al.
Hiroshima University
11:30-11:40

-  Break -




Optical and Wireless Chair: J. He


11:40-12:00
7
An Embedded Modulation of Silicon Germanium FIN-LED - A simulation study
J. Kwon et al.
Seoul National
University
12:00-12:20
8
Predicting Key Parameters of Inductive Power Links
S. Raju et al.
HK UST 
12:20-14:00

- Lunch Break -




Aging and Degradation Chair: M. Miura-Mattausch


14:00-14:40
9
Invited Keynote: Interaction of Bloch Carrier and Bound State in the Reliability Modeling
Y.J. Park and
S. Choi
Seoul National
University
14:40-15:00
10
Development of Unified Predictive NBTI Model and its Application for Circuit Aging Simulation
C. Ma et al.
Hiroshima University, STARC
15:00-15:20
11
Effects of Nonlocal Concentration of Carriers in the Oxide for NBTI Simulation
S. Rhee et al.
Seoul National
University
15:20-15:40

-  Break -




Fabrication Variation Chair: Y. J. Park


15:40-16:00
12
Parameter Extraction for Statistical Variation of HV-MOSFETs
Y. Ueda et al.
Ricoh, STARC
16:00-16:20
13
Analysis of Gate-Length Dependence of MOSFET Random Variation by Using HiSIM-RP
S. Kumashiro
et al.
Renesas Electronics
16:20-16:40
14
Random Dopant Fluctuation Effects on Double Gate Tunneling FET Performance
Y. Zhu et al.
Peking University
Shenzhen
16:40-16:50

Closing: H.J. Mattausch (Workshop Chair)