U.S. - Japan Collaboration Workshop
(Phase-1)
Tuesday, December 5 2023; 8:00 - 12:00 AM (JST)
Wednesday, December 6 2023; 8:00 - 12:00 AM (JST)
(Phase-1)
Tuesday, December 5 2023; 8:00 - 12:00 AM (JST)
Wednesday, December 6 2023; 8:00 - 12:00 AM (JST)
Online
The semiconductor industry is facing a number of challenges in building a stable supply chain. The importance of semiconductors was reaffirmed at the global level, and various initiatives were announced to revitalize and support the semiconductor industry, including investment in infrastructure development and human resource development for cutting-edge foundries. Against this backdrop, it is hoped that the creation of next-generation semiconductor technology and the further expansion of the industry will be achieved based on strong cooperation between Japan and the United States. As a phase 1 toward this goal, this workshop will discuss cutting-edge IC design technologies such as open source IC design, ecosystem construction, and human resource development. This workshop was supported by the U.S. Consulate in Fukuoka.
Application deadline is December 12. Please apply individually for DAY-1 and DAY-1the following form (you can also apply for only one of them).
[Participation fee] Free
[Notice] Simultaneous interpretation is available in English and at ZOOM Webinar.
DAY-1: Dec. 5th, 8:00-11:35 AM (JST)
8:00 - 8:05 Opening Remark and Overview of the Workshop, Mehdi Saligane, University of Michigan, Koji Inoue, Kyushu University
8:05 - 8:10 Welcome Remarks from the U.S. Consulate in Fukuoka
8:10 - 8:40 TBD, Steve Kosier, Skywater
8:40 - 9:10 The Emerging Ecosystem of Open-Source IC Design: IEEE SSCS Activities and Future Goals, Boris Murmann, Chair of the SSCS TC OSE, University of Hawaii
9:10 - 9:40 Human resource development for Semiconductor Technologies in Fukuoka, Koji Inoue, Fukuoka Semiconductor Reskilling Center/Kyushu University, Hideharu Kanaya, Kyushu University,
9:40 - 9:50 Break
9:50 - 10:20 Lab to Fab in the Cloud: Semiconductor Innovation at Amazon, David Pellerin, AWS
10:20 - 10:50 TBD, Kai Yick, Google Research ML
10:50 - 11:20 Analog and Mixed-Signal IC Design Automation, David Wentzloff, University of Michigan
11:20 - 11:30 Q&A + Panel Discussion
11:30 - 11:35 Conclusion, Mehdi Saligane, University of Michigan
DAY-2: Dec. 6th, 8:00-11:30 AM (JST)
8:00 - 8:05 Opening Remark and Overview of the Workshop, Mehdi Saligane, University of Michigan, Koji Inoue, Kyushu University
8:05 - 8:35 Innovation by Collaboration: CHIPS Alliance, Rob Mains, CHIPS Alliance, Linux Foundation
8:35 - 9:05 Developing CMOS+X Platforms for Artificial Intelligence and Beyond, Brian Hoskins, NIST
9:05 - 9:35 Agile-X: Agile Chip Design and Fabrication Platform, Makoto Ikeda, University of Tokyo
9:35 - 9:45 Break
9:45 - 10:15 The future of semiconductor : chips and chiplets, Dan J. Dechene, IBM Research
10:15 - 10:45 AI Chip Design Center – open hub for chip innovation -, Kunio Uchiyama, National Institute of Advanced Industrial Science and Technology
10:45 - 11:15 Democratizing EDA Tooling and Chip Design, Johan Euphrosine, Google (Tentative)
11:15 - 11:25 Q&A + Panel Discussion
11:25 - 11:30 Conclusion and Overview of the phase-2 workshop activities, Mehdi Saligane, University of Michigan, Koji Inoue, Kyushu University
[お問い合わせ] ic-design-ws 'at' slrc.kyushu-u.ac.jp （ 'at' を @ で置き換えてください）
No comments:
Post a Comment