[Conference] 33rd Austrochip 2025

Austrochip 2025

33rd Austrian Workshop on Microelectronics

September 25, 2025 – Linz, Austria

The TT workshop program

Conference Program

08:00 – 09:00 Coffee & Registration
09:00 – 09:15 Conference Opening
09:15 – 10:00 First Keynote-Address

• IHP OpenPDK and MPW: Pushing Open-Source EDA tools to Analog and RF Design René Scholz IHP – Leibniz Institute for high performance Microelectronics, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany

10:00 – 10:45 Second Keynote-Address

• Open-source SoC design using PULP Frank K. Gürkaynak ETH Zürich, IIS, ETZ J 60.1, Gloriastrasse 35, 8092 Zürich, Switzerland

10:45 – 11:00 Break
11:00 – 12:00 Paper Session I:
Session Chair: TBA, TBA

• Gain Expansion Generator based on a Reduced Conduction Angle for H-Band Applications Thomas Ufschlag, Benjamin Schoch, Lukas Gebert, Dominik Wrana, Axel Tessmann and Ingmar Kallfass University of Stuttgart (ILH), Fraunhofer Institute for Applied Solid State Physics IAF
• Greyhound: A Reconfigurable and Extensible RISC-V SoC and eFPGA on IHP SG13G2 Leo Moser, Meinhard Kissich, Tobias Scheipel and Marcel Baunach Graz University of Technology
• Comparison of Low Power Digitally Controlled Ring Oscillator Architectures in 12 nm FinFET Florian Schneider, Luca Avallone and Alicja Michalowska-Forsyth Infineon Technologies Austria AG Institute of Electronics (IFE), Graz University of Technology

12:00 – 12:30 Poster & Sponsor Pitch Session
12:30 – 14:00 Lunch
14:00 – 15:15 Paper Session II:
Session Chair: TBA, TBA

• A 150-GHz 9-dBm EIRP Open-Source FMCW Radar Chip in 130-nm BiCMOS Ghaith Al Sabagh, Georg Zachl and Harald Pretl Institute for Integrated Circuits and Quantum Computing, JKU Linz

• A CMOS Source-Coupled Relaxation Oscillator Achieving Close-in Phase Noise of −72.9 dBc/Hz at a 1 kHz Offset Baset Mesgari, Saeed Saeedi, Reinhard Feger and Horst Zimmermann Institute for Communications Engineering and RF-Systems, Johannes Kepler University Linz Faculty of Electrical and Computer Engineering, Tarbiat Modares University Christian Doppler Laboratory MWTH

• A FR3, 25 dBm Unbalanced MMIC GaAs Doherty Power Amplifier with Auxiliary Gate Voltage Modulation for Linearity Improvement Abdolhamid Noori, Fatemeh Abbassi, Christoph Wagner, Christian Fager and Gregor Lasser Chalmers University of Technology, Silicon Austria Labs

• A 72.7-90.4 GHz VCO with a Stacked NMOS based Tuning Network in 28nm FDSOI Waseem Abbas, Samir Aziri and Christoph Wagner Silicon Austria Labs

• A D-Band Active Down-Conversion Mixer with 80 GHz IF for FMCW Radar Frequency Extension Fatemeh Abbassi, Samir Aziri, Waseem Abbas, Christoph Wagner and Timm Ostermann Silicon Austria Labs, Institute for Integrated Circuits and Quantum Computing, JKU Linz

15:15 – 15:30 Break
15:30 – 16:45 Paper Session III:
Session Chair: TBA, TBA

• Design Automation of a Digitally Controlled Ring Oscillator using CUAS Cell Creator Framework Daniel Cerdà Holmager, Santiago Martin Sondón, Violeta Petrescu, Wolfgang Scherr and Johannes Sturm Carinthia University of Applied Sciences in Austria, CUAS
• Event-Based ADCs vs. Nyquist ADCs: Rethinking Performance Metrics Simon Dorrer, Anna Werzi, Bernhard A. Moser, Michael Lunglmayr and Harald Pretl Institute for Integrated Circuits and Quantum Computing, JKU Linz Institute of Signal Processing, JKU Linz
• Modeling Location-dependent Random Telegraph Noise for Circuit Simulators Florian Berger, Gerhard Landauer, Alicja Michalowska-Forsyth, Martin Flatscher, Philipp Greiner and Stefan Gansinger Institute for Electronics, Graz University of Technology Power and Sensor Systems, Infineon Technologies
• An 8.1-µW 12-bit Non-Binary Self-Clocked SAR-ADC in 130 nm Open-Source PDK Ali Olyanasab, Patrick Fath, Leonhard Schreiner, Christoph Guger and Harald Pretl g.tec medical engineering GmbH Institute for Integrated Circuits and Quantum Computing, JKU Linz
• SPAD Active Quenching/Resetting Circuit in 0.35-µm HV-CMOS Enabling 24V Excess Bias for PDP >90% Sherwin Nasirifar, Baset Mesgari, Christoph Ribisch, Saman Kohneh Poushi and Horst Zimmermann Institute of Electrodynamics, Microwave and Circuit Engineering, TU Wien Institute for Communications Engineering and RF Systems, JKU Linz Austrian Institute of Technology (AIT), Vienna Silicon Austria Labs

16:45 – 17:00 Conference Closing, Best Paper Award & Outlook Austrochip 2026

Aging Model for ASAP 7nm Predictive PDK

Neha Gupta¹, Lomash Chandra Acharya¹, Mahipal Dargupally¹, Khoirom Johnson Singh², Amit Kumar Behera¹, Johan Euphrosine³, Sudeb Dasgupta¹, Anand Bulusu¹

Aging Model Development for ASAP 7 nm Predictive PDK: Application in Aging-Aware Performance Prediction of Digital Logic and ADCs in Data Acquisition System

IEEE ISVLSI (2025)

DOI: 10.1109/ISVLSI65124.2025.11130265

1 Indian Institute of Technology, Roorkee, (IN)
2 Dhanamanjuri University, Manipur (IN)
3 Google, Tokyo (J)

Abstract: As semiconductor technology advances to sub- 10nm nodes, Design Technology Co-Optimization (DTCO) has emerged as an essential paradigm for co-optimizing processes and design methodologies. Although the ASAP 7nm Predictive PDK (Process Design Kit), which is a free and open-source academic PDK developed by the Arizona State University (ASU) research team, is a useful open-source platform for digital design research, it lacks key DTCO features such as reliability modeling, aging resilience, and security-aware co-design. In this article, we present our developed aging model for ASAP 7nm Predictive PDK and utilize it to evaluate the impact of transistor aging on the performance of digital timing logic and a memory cell which provides timing feedback from a DTCO point-of-view concerning standard cells and other reference circuit designing. In this work, different logic gates, benchmark circuits, N-stage ring oscillator and 6T SRAM bitcell are used as the representative of digital logic and memory cell, respectively. We further utilize our developed aging model to predict performance of an analog-to-digital converter in data acquisition systems. The developed aging model would be released for the research community for further improvement in design reliability and technology enhancement along with OPENROAD Tool flow.

Fig. (a) Flow chart for representing steps required to develop Verilog-A aging model 

for ASAP 7nm Predictive PDK (FinFET) process. 

(b) Inclusion of the developed aging model to incorporate aging impact in static timing analysis (STA).

FOSSEE eSim Marathon – Circuit Design & Simulation with IHP SG13G2

Design, Simulate, Showcase

Unlock Open-Source VLSI Design using eSim + IHP SG13G2 OpenPDK!!!

The eSim Marathon - Circuit Design & Simulation with IHP SG13G2 is a nationwide circuit design competition where participants use eSim, an open-source EDA tool developed by FOSSEE, IIT Bombay, to design and simulate circuits using the IHP OpenPDK for 130nm SG13G2 BiCMOS technology from IHP Microelectronics, Germany.

Key Highlights:

• Tool Used: eSim - a free and open-source alternative to commercial circuit design tools 
• OpenPDK Used: IHP SG13G2 - enables design of analog, digital, and RF circuits at 130 nm BiCMOS.
• Objective: Design, simulate, and submit functional analog/digital/mixed-signal circuits.
• Eligibility: Open to individuals - students, hobbyists, and early-career professionals.
• Learning Outcomes: Participants gain hands-on VLSI design experience using a real foundry OpenPDK, develop schematics, run simulations, and build documentation - entirely with open tools.

Register <https://esim-marathon.netlify.app/register/>

Timeline

Date	Activity	Description
1 Sept. - 15 Sept. 2025	Registration for the Marathon	Complete the participation form
16 Sept. 2025	Marathon Inauguration Webinar	FOSSEE Team will introduce through eSim, IHP and Marathon process
16 Sept. - 23 Sept. 2025	Literature Survey	Participants need to research the topic available in papers/journals on the web
23 Sept. 2025	Report Submission	Submit one-page research conclusion and circuit implementation plan
23 Sept. - 5 Oct. 2025	Implementation	Design, characterise and simulate using eSim platform
5 Oct. - 8 Oct. 2025	Report Submission & Documentation	Upload reference and actual circuit/waveform using eSim
25 Oct. 2025	Result Declaration (Provisional)	Announcement of provisional results

[paper] Human Language to Analog Layout

Ali Hammoud, Chetanya Goyal, Sakib Pathen, Arlene Dai, Anhang Li, Gregory Kielian,
and Mehdi Saligane

Human Language to Analog Layout Using GLayout Layout Automation Framework

ACM/IEEE MLCAD 

https://doi.org/10.1145/3670474.3685971

Abstract: Current approaches to Analog Layout Automation apply ML techniques such as Graph Convolutional Neural Networks (GCN) to translate netlist to layout. While these ML approaches have proven to be effective, they lack the powerful reasoning capabilities, an intuitive human interface, and standard evaluation benchmarks that have been improving at a rapid development pace in Large Language Models (LLMs). The GLayout framework introduced in this work translates analog layout into an expressive, technology generic, compact text representation. Then, an LLM is taught to understand analog layout through fine-tuning and in-context learning using Retrieval Augmented Generation (RAG). The LLM is able to successfully layout unseen circuits based on new information provided in-context. We train 3.8, 7, and 22 Billion parameter quantized LLMs on a dataset of less than 50 unique circuits, and text documents providing layout knowledge. The 22B parameter model is tuned in 2 hours on a single NVIDIA A100 GPU. The open-source evaluation set is proposed as an automation benchmark for LLM layout automation tasks, and ranges from 2-transistor circuits to aΔΣ ADC. The 22B model completes 70% of the tasks in the evaluation set, and passes DRC and LVS verification on 44% of evaluations with verified correct blocks up to 4 transistors in size.

FIG: Full process of translating user prompt to a final layout.

Acknowledgments: The authors would like to thank the open-source community for their support.

 

[paper] Differential Aging-Aware Static Timing Analysis

Lomash Chandra Acharya, Neha Gupta, Khoirom Johnson Singh, Mahipal Dargupally, Neeraj Mishra, 

Arvind Kumar Sharma, Ajoy Mondal, Venkatraman Ramakrishnan, 

Sudeb Dasgupta, and Anand Bulusu

DAAS: Differential Aging-Aware STA for Precise Timing Closure With Reduced Design Margin

in IEEE Transactions on Device and Materials Reliability

DOI: 10.1109/TDMR.2025.3603098

1.) Department of Electronics and Communication Engineering, IIT Roorkee (IN)
2.) Department of Electronics, Dhanamanjuri University, Imphal (IN)
3.) Department of Electronics and Electrical Engineering, BITS Pilani (IN)
4.) Semiconductor Technology and Systems Department, IMEC (B)
5.) EDA Group, Texas Instruments, Bengaluru (IN)
6.) OnSemi Technology, Bengaluru (IN)

Abstract : This article introduces DAAS, a Differential Aging-Aware Static Timing Analysis methodology built upon an Effective Current Source Model (ECSM). The primary objective is to achieve precise timing closure for digital integrated circuits while minimizing design margins. To achieve this goal, we employ a one-time aging simulation using a single MOS device-based approach. This approach estimates the change in threshold voltage (Vth) denoted by (Vth) in a MOS device under diverse operating conditions, such as supply voltage and temperature, in the presence of aging. The estimated value of (Vth) is then used to update the model coefficient of timing models for various combinational gates. These updated models are utilized to generate differential aging-aware standard cell library data in an industry-standard Liberty format. This data can be seamlessly integrated into common STA environments like Synopsys PrimeTime, facilitating the estimation of timing closure for designs with different blocks operating at varying voltages and temperature conditions. The proposed methodology eradicates the need for circuit-level aging simulation to generate differential aging-aware standard cell library data. It demonstrates an average error of 2.5% compared to conventional aging simulation on standard cells using the STMicroelectronics (STM) 28nm CMOS process. Furthermore, the method significantly reduces the required number of SPICE/aging simulations by approximately 99.984% to generate differential aging-aware standard cell library characterization data. Further, we demonstrate the versatility of the proposed DAAS methodology for the generation of standard cell library data in the case of PDK migration and different device variants without performing full SPICE-level simulations.

FIG: Representation of the approach used to model a standard cell 

with transistor topology of a buffer and its terminal transitions as a test case.

[Education Corner] Tinkering with CMOS Circuits

P. Kinget

Tinkering with CMOS Circuits at the Lunch Table with MOSbius

[Education Corner]

in IEEE Solid-State Circuits Magazine, vol. 17, no. 3, pp. 72-78, Summer 2025

doi: 10.1109/MSSC.2025.3583537

Abstract: Experimental validation is a critical step in any engineering discipline and doing lab experiments is an essential part of the formation of an engineer. Creating relevant experiments to train integrated-circuit designers has become difficult due to the lack of appropriate components. We designed the MOSbius chip and adapter PCB so learners can perform circuit labs with MOS transistor topologies that are relevant to modern transistor-level IC design. With MOSbius, students can experiment with customized CMOS circuits early on – without the challenges, delays, and cost of designing a custom integrated circuit. Yet, MOSbius serves as a great steppingstone towards full custom IC design courses.

Fig: An overview of the MOSbius platform. Students design and realize transistor-level MOS circuits

using on-chip-style topologies and evaluate them experimentally.

Acknowledgment: Many thanks to the MOSbius crew of enthusiastic current and former students: Longyi Li, Yunfan Gao, Zhuo Chen, Petar Barac, Ray Xu, Hongzhe Jiang, Cade Gleekel, Nico de la Cruz, Rosnel Alejandro Leyva-Cortes, Yuechen He, Jingde Hu, Qizhe Wu, Jingrui Li, Xianglin Pu, Yuntao Guo, and Andrew Chon. Thanks to Apple, Inc. for fabrication funding through the Columbia ELEN E6350 VLSI Design Lab course. Thanks to Yannis Tsividis (Columbia), John Pigott (NXP), Babak Soltanian (Tayen.Ai), Jianxun Zhu (Analog Devices, Inc.), Jared Zerbe (Apple), Eric Smith (Apple), Doug Mercer (ADI), and many others for engaging discussions and sharing of ideas.

[paper] Geometrical variability in FinFETs

C. Medina-Bailon, J.L. Padilla, L. Donetti, C. Navarro, C. Sampedro, F. Gamiz,

Geometrical variability impact on the gate tunneling leakage mechanisms in FinFETs,

Solid-State Electronics, 2025, 109212,

ISSN 0038-1101,

DOI: 10.1016/j.sse.2025.109212.

Abstract: Given the critical role that quantum tunneling effects play in the behavior of nanoelectronic devices, it is essential to investigate the influence and restraints of these phenomena on the overall transistor performance. In this work, a previously developed gate leakage model, incorporated into an in-house 2D Multi-Subband Ensemble Monte Carlo simulation framework, is employed to analyze the leakage current flowing across the gate insulator. The primary objective is to evaluate how variations in key geometrical parameters (specifically, gate oxide and semiconductor thicknesses dimensions) affect the magnitude and bias dependence of tunneling-induced leakage. Simulations are performed on a representative FinFET structure, and the results reveal that tunneling effects become increasingly pronounced at low gate voltages in devices with thinner oxides and thicker semiconductor thickness. These findings underscore the relevance of incorporating quantum tunneling mechanisms in predictive modeling of advanced transistor architectures.

Fig: Schematic FinFET device herein analyzed with confinement and transport directions (011) and <011>, respectively, and all the constant and varying geometrical parameters. Although FinFET is a 3D structure, it can be studied in a 2D approach, considering high aspect ratio fins (H>>TSi). In this 2D system, x and z are the transport and confinement directions, respectively; whereas y corresponds to the infinite direction. The 1D Schrödinger equation is solved for each grid point in the transport direction, and BTE is solved by the MC method in the transport plane.

IEEE SSCS DL at NXP Semiconductors, Munich

IEEE SSCS Distinguished Lecture

at NXP Semiconductors, Munich

Alvin Loke 

"The Road to Gate-All-Around and Its Impact on Analog Design"

Date/Time: 

11 Sep 2025 04:00 PM CEST to 06:30 PM CEST

Location: 

Schatzbogen 7; Munich, Bayern, Germany 81829

Building: NXP Semiconductors Germany GmbH

Host:

Germany Section Chapter, SSC37

Co-sponsored by NXP Semiconductors

Contact:

Event Host

FREE REGISTRATION 

Abstract: Despite the much debated end of Moore's Law, CMOS scaling still maintains economic relevance with 3nm finFET SoCs already in the marketplace for over a year and 2nm gate-all-around SoCs anticipated this year. Modest feature size reduction and design/technology innovations co-optimized for primarily logic scaling continue to offer compelling node-to-node power, performance, area, and cost benefits. In this tutorial, we will start with a walk through memory lane, recounting a brief history of transistor evolution to motivate the migration from the planar MOSFET to the fully depleted FinFET. We will summarize the key process technology elements that have enabled the finFET CMOS nodes, highlighting the resulting device technology characteristics and challenges. This will set the context for motivating the introduction of the gate-all-around transistor architecture, namely nanoribbons or nanosheets, and unveiling the magic of how these devices are fabricated. We will then shift to summarize the challenges that CMOS technology scaling has imposed on analog design. To address the growing effort required for analog/mixed-signal design closure, we will cover design strategies on how analog design has adapted and thrived throughout decades of increasingly unfriendly CMOS scaling, including the migration to heterogeneous integration as prophesied by Gordon Moore's seminal 1965 paper.

Biography: Alvin Loke is a Senior Principal Engineer at Intel, San Diego, working on analog design/technology co-optimization for Intel's Angstrom-era CMOS. He has previously worked on CMOS nodes spanning 250nm to 2nm at Agilent, AMD, Qualcomm, TSMC, and NXP. He received a B.A.Sc. in engineering physics from the University of British Columbia, and M.S. and Ph.D. in electrical engineering from Stanford. After several years in CMOS process integration, Alvin has since worked on analog/mixed-signal design focusing on a variety of wireline links, design/model/technology interface, and analog design methodologies. Alvin has been an active IEEE Solid-State Circuits Society (SSCS) volunteer since 2003, having served as Distinguished Lecturer, AdCom Member, CICC Committee Member, Webinar Chair, Denver and San Diego Chapter Chair, as well as JSSC, SSCL, and Solid-State Circuits Magazine Guest Editor. He currently serves as the VLSI Symposium Secretary, SSCS Global Chapters Chair, and again as Distinguished Lecturer. Alvin has authored over 70 publications including the CICC 2018 Best Paper and invited short courses at ISSCC, VLSI Symposium, CICC, and BCICTS. He holds 29 US patents and recently received the ISSCC 2024 Outstanding Forum Speaker Award.

[paper] An Open-Source AMS Circuit Optimization

Z. Li and A. Chan Carusone

An Open-Source AMS Circuit Optimization Framework Based on Reinforcement Learning: 

From Specifications to Layouts

in IEEE Access, vol. 12, pp. 150032-150045 (2024) 

DOI: 10.1109/ACCESS.2024.3478832

Abstract: This paper presents a fully open-sourced AMS integrated circuit optimization framework based on reinforcement learning (RL). Specifically, given a certain circuit topology and target specifications, this framework optimizes the circuit in both schematic and post-layout phases. We propose using the heterogeneous graph neural network as the function approximator for RL. Optimization results suggest that it can achieve higher reward values with fewer iterations than the homogeneous graph neural networks. We demonstrate the applications of transfer learning (TL) in optimizing circuits in a different technology node. Furthermore, we show that by transferring the knowledge of schematic-level optimization, the trained RL agent can optimize the post-layout performance more efficiently than optimizing post-layout performance from scratch. To showcase the workflow of our approach, we extended our prior work to optimize latched comparators in the SKY130 and GF180MCU processes. Simulation results demonstrate that our framework can satisfy various target specifications and generate LVS/DRC clean circuit layouts.

FIG: Proposed AMS IC optimizer overview. 

The picture is adapted from [Z. Li and A. C. Carusone; 2023]

Acknowledgment: The authors would like to thank Dr. Hossein Shakiba from Huawei Technologies
for his valuable discussions throughout this project.

[REF] Z. Li and A. C. Carusone, "Design and optimization of low-dropout voltage regulator using relational graph neural network and reinforcement learning in open-source SKY130 process," in Proc. IEEE/ACM Int. Conf. Comput. Aided Design (ICCAD), Oct. 2023, pp. 1–9.

[mos-ak] Join the ICMC 2026 Organizing Team

International Compact Modeling Conference (ICMC) 2025 was a great success - thank you to everyone who contributed!  We're excited to announce that preparations are already underway for the next edition, taking place July 30–31, 2026 in Long Beach, California.

We are currently seeking enthusiastic volunteers to join the ICMC2026 organizing committees. If you're interested in helping shape next year's event, please complete the survey linked below:

https://survey.zohopublic.com/zs/bQfsUq

Submission deadline: August 25, 2025

📩 For questions about available roles, feel free to contact:

Shahed Reza, ICMC2026 General Chair or

Gert-Jan Smit, ICMC2026 Technical Program Chair

We look forward to your participation!

Thank you,
Leigh Anne Clevenger , Si2, on behalf of the ICMC2026 Organizing Committee

[mos-ak] [Final Program] 9th Sino MOS-AK Workshop Shenzhen

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

9th Sino MOS-AK Workshop Shenzhen

August 14-16, 2025

We are pleased to invite you to participate in the 9th Sino MOS-AK Workshop, a premier forum for researchers, engineers, and industry professionals engaged in the device simulations, compact modeling, Verilog-A standardization, and advanced circuit design. This year's workshop will be hosted at SUSTech in Shenzhen, offering a dynamic program that blends cutting-edge research with practical insights. 

Venue:

• Southern University of Science and Technology (SUSTech), Shenzhen, China

Workshop Agenda <https://www.mos-ak.org/shenzhen_2025/>

• Aug.14 Room 103
• Tutorial: Millimeter-wave Radar Technologies for Future Smart Home Applications
• 深圳器件模型国际会议 access link：https://www.koushare.com/live/details/45275
• Aug.15 Room 103
• Special Session: Advanced GaN Device Modeling and Circuit Design
• 深圳器件模型国际会议 access link：https://www.koushare.com/live/details/45275
• Aug.15 Room 104
• Special Session: Artificial Intelligence in Device Modeling and Circuit Design
• 深圳器件模型国际会议 access link：https://www.koushare.com/live/details/45276
• Aug.16 Room 103
• Special Session: Device Modeling and Circuit Designs for Extreme Temperatures
• 深圳器件模型国际会议 access link：https://www.koushare.com/live/details/45275
• Aug.16 Graduate Student Poster Session

We look forward to your participation in this vibrant exchange of ideas and innovations. For registration and inquiries, please contact: music@sustech.edu.cn

-- Min Zhang and W.Grabinski on the behalf of International MOS-AK TPC Committee

---

Enabling Compact Modeling R&D Exchange

www.mos-ak.org

---

WG11082025

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[book] Guide to Characteristics and Characterization of Semiconductor Surfaces

Guide to Characteristics and Characterization 

of Semiconductor Surfaces

By: Jerzy Ruzyllo (Penn State University, USA)

https://doi.org/10.1142/12792 | May 2025 | Pages: 220

This comprehensive compendium explores aspects of semiconductor surface characteristics and characterization from the perspective of applied semiconductor device research and process development, rather than an in-depth coverage of surface science related issues. It provides guidance to the features of semiconductor surfaces affecting performance of the practical semiconductor devices, as well as selection of methods used to characterize those features.

Based on the author's over thirty years of research and graduate advising in semiconductor surface processing and characterization, this unique reference text addresses the needs of graduate students, researchers and industry professionals who are familiar with semiconductor engineering and would like to learn about the practical aspects of semiconductor surface characteristics, processing techniques, and characterization methods used in device process development, process diagnostics and monitoring.

• FRONT MATTER i–xv
• Chapter 1: Surface as a Part of Semiconductor Device Material System 1–14
• Chapter 2: Effect of Surface on Characteristics of Semiconductor Materials 15–36
• Chapter 3: Interactions of Semiconductor Surfaces 37–56
• Chapter 4: Characteristics of Semiconductor Surface Defining its Condition 57–68
• Chapter 5: Surface Effects in Semiconductor Devices 69–79
• Chapter 6: Surface Processing in Semiconductor Device Technology 81–117
• Chapter 7: Semiconductor Surface Characterization Methods 119–152
• Chapter 8: Characterization of Semiconductor Surfaces in Process Monitoring 153–176
• BACK MATTER 177–201

[mos-ak] IEEE SSCS-EDS South Brazil Chapter DL - IHP OpenPDK Initiative – Technology · Devices · Applications

The IEEE SSCS-EDS South Brazil Chapter, chaired by Juan Pablo Martinez Brito, PhD, to host Wladek Grabinski, PhD, a global expert in SPICE modeling and open-source IC design, for a Distinguished Lecture:

IHP OpenPDK Initiative – Technology · Devices · Applications

Date: August 13th, 2025

Time: 14h00 (GMT-3, Brasília)

IEEE SSCS-EDS South Brazil Chapter YouTube Channel

http://www.youtube.com/c/sscsedssouthbrazil

Dr. Grabinski will explore the growing role of FOSS CAD/EDA tools and OpenPDKs in strengthening the semiconductor ecosystem and enabling accessible IC design worldwide.

Thanks to the support of Unisinos, Federal University of Rio Grande do Sul, and UNIPAMPA Universidade Federal do Pampa RS, and to all the volunteers and engineers helping grow our regional chapter. Also, thank you to the chapter Board: Sandro Binsfeld Ferreira, Tiago Oliveira Weber, and Paulo César C. de Aguirre, and Professors Gilson Wirth and Sergio Bampi for the advice.

Looking forward to engaging with students, researchers, and professionals from across Brazil and beyond.

Attachments:

Event Calendar Invite

 Add Event to Calendar

 iCal
 Google Calendar

South Brazil Section Jt. Chapter,SSC37/ED15

#OpenPDK #SPICE #CompactModeling #Semiconductors #IEEE #ICDesign #FOSS #AnalogDesign #PDK #CMOS #IHP #SkyWater #GF #EDA #SouthAmericaSemiconductors #MOSAK #EDS #SSCS #UFRGS #Unisinos #Unipampa

WG060825

Low Cost Open Source MPW Access with IHP 130nm BiCMOS OpenPDK

Low Cost Open Source MPW Access 

with IHP 130nm BiCMOS OpenPDK

Terms and conditions
The mentioned prices below refer to the open-source designs, where all the views are compatible with the open source EDA tools.

For customers who do not wish to disclose their IP, we offer participation in the OpenMPW program at a 20% discount off the regular price, as the wafers can be shared with other customers. The turn around processing time is approx. 6 months for SG13CMOS and 8 months for SG13G2. Our/IHP basic offer contains 20 bare die samples. It is also possible to rent the wafer for measurements. Packaging will be offered on request (additional fee can be applied). 

Request/reserve your MPW IC Chip area online

Date of the upcoming MPW tapeout:  Optional run in November 2025, SG13CMOS

Total amount used by all customers: tbd

Price per mm²:

SG13CMOS – the initial price is 1500 EUR/mm² and it will scale down to 1000 EUR/mm² 

if the total area requested by all customers will be higher than 150 mm²

SG13G2 – fully featured G2 with AL BEOL at approx. 2800 EUR/mm²

SG13G2 Technology overview:

• High speed SiGe HBT's featuring transit frequency (fT) of 350 GHz
• Low/High voltage CMOS devices
• 78 standard cells, IO-cells, a few fixed size SRAM
• Regular ESD diodes, NMOS clamps
• S-varicap
• Schottky diodes
• Polysilicon resistors, tap devices
• MIM capacitor
• 7 layer aluminium BEOL with 2 thick 3um top metal layers
• [NB] SG13CMOS does not provide HBT's

IHP-Open-PDK Overview

• Symbols for Xschem/Qucs-S
• Ngspice models
• Xyce models
• Klayout support for layout, PyCells, DRC and LVS
• Magic basic support (more to be finished until the end of the year)
• OpenROAD-flow-script support
• OpenEMS EM solver support
• Measurements RAW data in MDM format

Click here to open the IHP 130nm BiCMOS Open Source PDK documentation link

<https://ihp-open-pdk-docu.readthedocs.io/en/latest/index.html>

Click here to open the standard MPW price information

<https://www.ihp-microelectronics.com/services/research-and-prototyping-service/mpw-prototyping-service/schedule-price-list>

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[rsvNumerics] hands-on transistor sizing for analog ICs

rsvNumerics – info@rsvn.ch

Copyright © 2025 rsvNumerics – All Rights Reserved

rsvNumerics provides concepts, guidance and software tools for sizing transistors in integrated circuits with an easy-to-learn methodology. Whether you are a novice or an expert, you can benefit from our methodology and dimension your devices in no time, serving as a near-perfect starting point for your verification. Moreover, our methodology is not limited to a few predefined circuit topologies; it works for literally any circuit in any application.

Constant-𝑔𝑚 Biasing Circuit Example 

rsvNumerics in Circuit Design General, SizingTool

The schematic of the constant-𝑔𝑚 bias circuit is shown above. It consists of two cross-coupled current mirrors, where one of the source contacts, e.g. of an NMOS transistor, is degenerated by a source resistor. This results in a unique operating point of the circuit other than zero current, which defines the pass current in the two branches.

The corresponding settings of SizingTool 3 for transistor 𝑁𝑀0 and for transistor 𝑁𝑀1 are given in Fig above. Once the drain currents for a constant-𝑔𝑚 biasing block are known, we can use the information when designing any other transistor with derived source current. However, there its drain current has to be readjusted each time the process corner is changed to reflect for constant-𝑔𝑚 biasing, which is tedious, and is addressed by the current weighing option.

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[paper] Gradient Minimization in Layout Patterns for Analog Circuits

Isaac Bruce, Michael Sekyere, Ruohan Yang, Saeid Karimpour, Colin C. McAndrew, Degang Chen

Gradient Minimization in Layout Patterns for Analog Circuits

Circuits, Systems, and Signal Processing. 1-22.

DOI: 10.1007/s00034-025-03158-x

1 Department of Electrical and Computer Engineering, Iowa State University, Ames, IA, USA

 

Abstract: In this paper, we present an algorithm to generate the layout of a pair of devices A and B for a given matching ratio r and total unit cell count N that minimizes the mismatch due to systematic gradient effects. The algorithm relies on simple reflections and rotations of an initial optimized pattern across 4 quadrants. The approach cancels all odd-order systematic gradients and minimizes 2nd order systematic gradients. The method can easily be extended to cancel higher-order even gradient effects. The validity of the proposed algorithm is demonstrated via numerical simulations. Additionally, an electrothermal simulation of a set of layouts is run to further validate the proposed layout generation scheme.

FIG: Layout of circuit design with heat sources and current sources 

for the optimal transistor array pattern.

[mos-ak] 一生一芯 2025 Summer Launch Conference

 One Student, One Chip

2025 Summer Launch Conference

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🗓 Conference Details

• Date & Time: July 21st (Monday), 14:30
• Location: Room 104, Mingde Campus, Shenzhen University, Nanshan District, Shenzhen, Guangdong Province
• Participation: Online registration open until July 19th, 23:59
• Live Stream: Bilibili Live Broadcast Link

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🎓 About the Project

The "One Student One Chip" (一生一芯, ysyx.org) program is an open-source, free, and public training platform aimed at developing full-stack engineers proficient in both hardware and software. It's designed for lifelong learners of all ages—from primary school to university—without limitations. Students are guided in designing and implementing a RISC-V CPU, using:

• Chisel (hardware description language)
• FPGA tools
• DK development environment

They explore concepts spanning:

• Digital logic
• RTL design
• Computer architecture
• Operating systems
• Compilers

Since its 2019 launch, the program has involved over 12,000 students, with backing from top universities including Tsinghua, Peking, and Fudan.

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🌟 Key Highlights for 2025

1. New teaching materials with a hierarchical learning model (EDCBA) to enhance learning efficiency
2. Post-course chip design program with ECOS Studio tools and open-source test platforms
3. Launch of MOLI Learning Platform, offering curated courses from universities like MIT, Tsinghua, and Peking University

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🏫 Supporting Institutions

• Tsinghua University
• Peking University
• Fudan University
• Zhejiang University
• Shanghai Jiao Tong University
• University of Science and Technology of China
• Harbin Institute of Technology
• National University of Defense Technology

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[mos-ak] [Media Note] MOS-AK Workshop, London, July 11, 2025

MOS-AK Workshop 2025 Held at London Metropolitan University [MOS-AK Media Note]

The MOS-AK Compact Modelling Workshop was successfully hosted on July 11, 2025, at London Metropolitan University, bringing together a diverse group of researchers, engineers, and industry professionals to explore recent advances in compact modelling, semiconductor technologies, and circuit simulation. This in-person event marked a valuable opportunity for participants to reconnect face-to-face, exchange ideas, and foster collaboration across institutions and disciplines.

The workshop featured a distinguished panel of presenters from academia, research institutions, and industry. These experts delivered high-quality technical talks covering a broad range of cutting-edge topics in compact device modelling, circuit design, and emerging applications. The presentations covered innovative research and development in the following areas:

• Open PDK Progress: "IHP-Open-PDK Review: Present Status and Future Directions" Dr. Krzysztof Herman -  IHP Leibniz Institute for High Performance Microelectronics

• Open PDK Progress: "The Application of FOSS Tools in the Design of IHP Open-Access 130nm BiCMOS RF Integrated Circuits" Prof. Mike Brinson -  London Metropolitan University

• Open PDK Progress: "Presentation and Evaluation of the 1st IHP Open Source Analog Certificate Course" Phillip Ferreira Baade-Pedersen -  IHP Leibniz Institute for High Performance Microelectronics

• Biomedical Sensing: "Non-invasive Biomedical Sensor for Dehydration Monitoring" Prof. Bal Virdee and Innocent Lubangakene London Metropolitan University (UK)

• Quantum Modelling: "Compact Quantum Dot Models for Analog Microwave Co-Simulation"
  Lorenzo Peri -  Quantum Motion and University of Cambridge

• Cryogenic Electronics: "Deep-Cryogenic Device Characterisation in a CMOS Foundry Process"
  Grayson Noah -  Quantum Motion

• Compact Modelling: "Developments of Compact Models for Source-Gated Devices"
  Dr. Patryk Golec -  École Polytechnique, Paris

• Display and Bio Circuits: "Area- and Energy-Efficient Current-Mode Pixel Circuits for High-Performance Display and Life Science Applications"
  Dr. Eva Bestelink -  University of Surrey

• Novel Transistor Behaviour: "Opportunities for Modelling Off-State Behaviour in Polysilicon Contact-Controlled Transistors"
  Prof. Radu A. Sporea -  University of Surrey

Each session stimulated thoughtful discussion and knowledge sharing among attendees, reinforcing the relevance of compact modelling in enabling innovation across semiconductor technologies.

The event was organized by London Metropolitan University with the support of the Institution of Engineering and Technology (IET) and the IEEE Electron Devices Society, and was generously sponsored by the IHP Leibniz Institute for High Performance Microelectronics.

A total of 35 delegates attended the workshop, representing a mix of academia, research labs, and industry. The workshop concluded with a networking drinks reception, providing attendees a relaxed environment to engage in informal discussions, build professional connections, and explore collaborative opportunities.

-- Prof. Bal Virdee, Prof. Mike Brinson and W.Grabinski for Extended MOS-AK Committee

WG150725

[mos-ak] [Final Program] 22nd MOS-AK/ESSERC Workshop in Munich (D) Sept. 8, 2025

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

MOS-AK/ESSERC Workshop in Munich

September 8, 2025

Scheduled consecutive 22nd MOS-AK/ESSERC SPICE/Compact Modeling T2 Workshop organized in Munich, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and FOSS CAD/EDA tool developers and vendors. The content will be beneficial for anyone who needs to learn what is really behind the FOSS CAD/EDA IC simulation in modern device models in OpenPDKs. The MOS-AK workshop program is available online: 

<https://www.mos-ak.org/munich_2025/>

It will be followed by ESSERC T2 Tutorial "Design and Simulation of Analog/RF Integrated Circuits with Open-Source CAD Tools and Process Design Kits". T2 tutorial explores how FOSS CAD/EDA tools and OpenPDKs empower IC designers. T2 also introduces ACM2, a compact, physics-based MOSFET model, with hands-on guidance on design parameter extraction for analog/RF circuit applications using the IHP OpenPDK 130nm BiCMOS process.

Online Registration is open (Early: until Friday July 18, 2025 (23:59 CEST))

any related enquiries can be sent to registration@mos-ak.org

-- W.Grabinski on the behalf of International MOS-AK TPC Committee

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Enabling Compact Modeling R&D Exchange

www.mos-ak.org

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WG140725

[mos-ak] [C4P] Austrochip 2025

Call for Papers – Austrochip 2025

Submission Deadline: July 24, 2025

We, JKU, Local Organizer and Host, are excited to invite submissions for Austrochip 2025 – The 33rd Austrian Workshop on Microelectronics, happening on September 24-25, 2025, in Linz, Austria. This workshop is a key platform for sharing advancements in microelectronics, connecting researchers, and fostering collaboration. If you're working on innovative designs, methodologies, or applications, we'd love to see your work!

For submission details and guidelines, visit: https://iic.jku.at/austrochip/pages/call-for-papers.html

Join us for an exciting workshop and conference on the future of microelectronics!