Lomash Chandra Acharya, Neha Gupta, Khoirom Johnson Singh, Mahipal Dargupally, Neeraj Mishra,
Arvind Kumar Sharma, Ajoy Mondal, Venkatraman Ramakrishnan,
Sudeb Dasgupta, and Anand Bulusu
DAAS: Differential Aging-Aware STA for Precise Timing Closure With Reduced Design Margin
in IEEE Transactions on Device and Materials Reliability
DOI:
10.1109/TDMR.2025.3603098
1.) Department of Electronics and Communication Engineering, IIT Roorkee (IN)
2.) Department of Electronics, Dhanamanjuri University, Imphal (IN)
3.) Department of Electronics and Electrical Engineering, BITS Pilani (IN)
4.) Semiconductor Technology and Systems Department, IMEC (B)
5.) EDA Group, Texas Instruments, Bengaluru (IN)
6.) OnSemi Technology, Bengaluru (IN)
2.) Department of Electronics, Dhanamanjuri University, Imphal (IN)
3.) Department of Electronics and Electrical Engineering, BITS Pilani (IN)
4.) Semiconductor Technology and Systems Department, IMEC (B)
5.) EDA Group, Texas Instruments, Bengaluru (IN)
6.) OnSemi Technology, Bengaluru (IN)
Abstract
: This article introduces DAAS, a Differential Aging-Aware Static Timing Analysis methodology built upon an Effective Current Source Model (ECSM). The primary objective is to achieve precise timing closure for digital integrated circuits while minimizing design margins. To achieve this goal, we employ a one-time aging simulation using a single MOS device-based approach. This approach estimates the change in threshold voltage (Vth) denoted by (Vth) in a MOS device under diverse operating conditions, such as supply voltage and temperature, in the presence of aging. The estimated value of (Vth) is then used to update the model coefficient of timing models for various combinational gates. These updated models are utilized to generate differential aging-aware standard cell library data in an industry-standard Liberty format. This data can be seamlessly integrated into common STA environments like Synopsys PrimeTime, facilitating the estimation of timing closure for designs with different blocks operating at varying voltages and temperature conditions. The proposed methodology eradicates the need for circuit-level aging simulation to generate differential aging-aware standard cell library data. It demonstrates an average error of 2.5% compared to conventional aging simulation on standard cells using the STMicroelectronics (STM) 28nm CMOS process. Furthermore, the method significantly reduces the required number of SPICE/aging simulations by approximately 99.984% to generate differential aging-aware standard cell library characterization data. Further, we demonstrate the versatility of the proposed DAAS methodology for the generation of standard cell library data in the case of PDK migration and different device variants without performing full SPICE-level simulations.
FIG: Representation of the approach used to model a standard cell
with transistor topology of a buffer and its terminal transitions as a test case.
