C. Medina-Bailon, J.L. Padilla, L. Donetti, C. Navarro, C. Sampedro, F. Gamiz,
Geometrical variability impact on the gate tunneling leakage mechanisms in FinFETs,
Solid-State Electronics, 2025, 109212,
ISSN 0038-1101,
DOI: 10.1016/j.sse.2025.109212.
Abstract: Given the critical role that quantum tunneling effects play in the behavior of nanoelectronic devices, it is essential to investigate the influence and restraints of these phenomena on the overall transistor performance. In this work, a previously developed gate leakage model, incorporated into an in-house 2D Multi-Subband Ensemble Monte Carlo simulation framework, is employed to analyze the leakage current flowing across the gate insulator. The primary objective is to evaluate how variations in key geometrical parameters (specifically, gate oxide and semiconductor thicknesses dimensions) affect the magnitude and bias dependence of tunneling-induced leakage. Simulations are performed on a representative FinFET structure, and the results reveal that tunneling effects become increasingly pronounced at low gate voltages in devices with thinner oxides and thicker semiconductor thickness. These findings underscore the relevance of incorporating quantum tunneling mechanisms in predictive modeling of advanced transistor architectures.
Keywords: Geometrical variability; Gate leakage mechanism; Direct oxide tunneling; Trap assisted tunneling; Leakage current; MS-EMC; FinFET
Fig: Schematic FinFET device herein analyzed with confinement and transport directions (011) and <011>, respectively, and all the constant and varying geometrical parameters. Although FinFET is a 3D structure, it can be studied in a 2D approach, considering high aspect ratio fins (H>>TSi). In this 2D system, x and z are the transport and confinement directions, respectively; whereas y corresponds to the infinite direction. The 1D Schrödinger equation is solved for each grid point in the transport direction, and BTE is solved by the MC method in the transport plane.
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