[paper] 3nm Nano-Sheet FETs

Etienne SICARD* and Lionel TROJMAN**

Introducing 3-nm Nano-Sheet FET technology in Microwind

hal-03377556: Submitted on 14 Oct 2021

  

*INSA-Dgei, Toulouse (F)
**ISEP, Issy les Moulineaux (F)

Abstract: This paper describes the implementation of the novel Nano-sheet FET (NS-FET) for the 3-nm CMOS technology node in Microwind. After a general presentation of the electronic market and the roadmap to the atomic scale, design rules and basic metrics for the 3-nm node are presented. Concepts related to the design of NS-FET and design for manufacturing are also described. The performances of a ring oscillator, basic cells, sequential cells and a 6-transistor RAM memory are also analyzed.

Fig: A simple 3-stage ring oscillator based on compiled inverters “Fast” mode.

[ref] MICROWIND software allows the designer to simulate and design an integrated circuit at physical description level. Born in Toulouse (France), Microwind is an innovative CMOS design tool for educational market.

[paper] 2D-SFET Based SRAMs

Niharika Thakuria, Graduate Student Member, IEEE, Daniel Schulman, Member, IEEE, Saptarshi Das, Member, IEEE, and Sumeet Kumar Gupta, Member, IEEE

2D Strain FET (2D-SFET) Based SRAMs - Part I: Device-Circuit Interactions

 IEEE TED, vol. 67, no. 11, pp. 4866-4874, Nov. 2020

DOI: 10.1109/TED.2020.3022344.

Abstrat: In this article, we analyze the characteristics of a recently conceived steep switching device 2-D Strain FET (2D-SFET) and present its circuit implications in the context of 6T-SRAM. We discuss the dependence of 2D-SFET characteristics on key design parameters, showing up to 2.7× larger ON-current and 35% decrease in subthreshold swing when compared to 2D-FET. We analyze the performance of 2D-SFET (as drop-in replacement for standard 2D-FET) in 6T-SRAM for a range of design parameters and compare those to 2D-FET 6T-SRAM. 2D-SFET 6T-SRAM achieves up to 5.7% lower access time, 63% higher write margin, and comparable hold margin, but at the cost of comparable to 11% lower read stability and 16% increase in write time. In Part II of this article, we mitigate the read stability issues of 2D-SFET SRAMs by proposing VB-enabled SRAM designs.

Fig: 2D-SFET model with bandgap reduction and 2-D-electrostatics [18]. COX, CGS/D,F, CIT, and CGB are oxide, gate (G) to source (S)/drain (D) fringe, trap, and PE capacitance, respectively. VFB, and VFBS are flat-band voltage of G and back contact. VQFL(VS,VD) is S/D quasiFermi level. ΔEG(VG'B) is VGB dependent bandgap change, τEG is strain transduction delay, and REG is resistance used to model τEG. ΔEG(τEG) is final bandgap reduction considering τEG, used for calculating channel charge, QCH(ΔEG(τEG)).

Aknowlegement: This work was supported in part by NSF under Grant 1640020, in part by Nanoelectronics Research Corporation (NERC), and in part by Semiconductor Research Corporation (SRC) under Grant 2699.003

[paper] Memory Technology – A Primer for Material Scientists.

Schenk, Tony, Milan Pesic, Stefan Slesazeck, Uwe Schroeder, and Thomas Mikolajick

Memory Technology–A Primer for Material Scientists

Reports on Progress in Physics (2020)

Abstract - From our own experience in the group, we know that there is quite a gap to bridge between scientists focused on basic material research and their counterparts in a close-to-application community focused on identifying and solving final technological and engineering challenges. In this review, we try to provide an easy-to-grasp introduction to the field of memory technology for materials scientists. As an understanding of the big picture is vital, we first provide an overview about the development and architecture of memories as part of a computer and point out some basic limitations that all memories are subject to. As any new technology has to compete with mature existing solutions on the market, today's mainstream memories are explained and the need for future solutions is highlighted. The most prominent contenders in the field of emerging memories are introduced and major challenges on their way to commercialization are elucidated. Based on these discussions, we derive some predictions for the memory market to conclude the paper.

TABLE OF CONTENTS

1. INTRODUCTION
2. OVERVIEW AND BASIC LIMITATIONS
3. COMMERCIALLY AVAILABLE MAINSTREAM MEMORIES

3.1. Static and Dynamic Random Access Memory (SRAM/DRAM)
3.2. Flash Memory and Solid-State Drive (SSD)
3.3. Magnetic Hard Disk Drives (HDD) and Magnetic Tapes
3.4. Outlook: Market Trends and Drivers

4. EMERGING MEMORIES

4.1. Resistance-based Read-out: Memory Concepts and Basic Considerations
4.2. Anion migration or valence change memory (VCM)
4.3. Cation migration or electrochemical metallization memory (ECM)
4.4. Phase change memory (PCM)
4.5. Magnetoresistive memory (MRM)
4.6. Ferroelectric Memory (FEM)
4.7. Miscellaneous

5. SUMMARY AND CONCLUSION

FIG: Evolution of the mainstream solutions for the respective memories classes. The introduction of Flash memory partially bridged a technology gap around the year 2009. Today, two types of so-called storage-class memories – a memory-type SCM (SCM 1) and a storage-type SCM (SCM 2) – were proposed to overcome the memory gap. NAND flash already fulfills the role of a mainstream SCM 2. For SCM 1, 3D XPoint could be a promising candidate, but is not a dominant mainstream memory. In future, we will likely see different types of SCMs and NV-RAM with different specifications as required by the respective application – because in the end, the overall system cost decides about the choice of the memory.

IMEC presented 22nm CMOS SRAM 0.099µm2 cell:

IMEC presented the world's first functional 22nm CMOS SRAM cells made using EUV lithography. The 0.099µm² SRAM cells are made with FinFETs. In its core EC program PULLNANO, IMEC works together with leading IC companies on future CMOS technologies. Key partners in 2009 are Intel, Micron, Panasonic, Samsung, TSMC, Elpida, Hynix, Powerchip, Infineon, NXP, Qualcomm, Sony, ST Microelectronics. With such concerted collaborations, the semiconductor industry is able to keep innovating and to follow Moore's momentum, noted Luc Van den hove, COO at IMEC.

Further information on IMEC can be found at www.imec.be