Aging Model for ASAP 7nm Predictive PDK

Neha Gupta¹, Lomash Chandra Acharya¹, Mahipal Dargupally¹, Khoirom Johnson Singh², Amit Kumar Behera¹, Johan Euphrosine³, Sudeb Dasgupta¹, Anand Bulusu¹

Aging Model Development for ASAP 7 nm Predictive PDK: Application in Aging-Aware Performance Prediction of Digital Logic and ADCs in Data Acquisition System

IEEE ISVLSI (2025)

DOI: 10.1109/ISVLSI65124.2025.11130265

1 Indian Institute of Technology, Roorkee, (IN)
2 Dhanamanjuri University, Manipur (IN)
3 Google, Tokyo (J)

Abstract: As semiconductor technology advances to sub- 10nm nodes, Design Technology Co-Optimization (DTCO) has emerged as an essential paradigm for co-optimizing processes and design methodologies. Although the ASAP 7nm Predictive PDK (Process Design Kit), which is a free and open-source academic PDK developed by the Arizona State University (ASU) research team, is a useful open-source platform for digital design research, it lacks key DTCO features such as reliability modeling, aging resilience, and security-aware co-design. In this article, we present our developed aging model for ASAP 7nm Predictive PDK and utilize it to evaluate the impact of transistor aging on the performance of digital timing logic and a memory cell which provides timing feedback from a DTCO point-of-view concerning standard cells and other reference circuit designing. In this work, different logic gates, benchmark circuits, N-stage ring oscillator and 6T SRAM bitcell are used as the representative of digital logic and memory cell, respectively. We further utilize our developed aging model to predict performance of an analog-to-digital converter in data acquisition systems. The developed aging model would be released for the research community for further improvement in design reliability and technology enhancement along with OPENROAD Tool flow.

Fig. (a) Flow chart for representing steps required to develop Verilog-A aging model 

for ASAP 7nm Predictive PDK (FinFET) process. 

(b) Inclusion of the developed aging model to incorporate aging impact in static timing analysis (STA).

[paper] Vertical Junction-Less Nanowire FETs

C. Maneux (University of Bordeaux), C. Mukherjee (CNRS), M. Deng (University of Bordeaux), G. Larrieu (CNRS), Y. WANG, B. Wesling, and H. Rezgui (University of Bordeaux)

Strategies for Characterization and Parameter Extraction of Vertical Junction-Less Nanowire FETs Dedicated to Design Technology Co-Optimization

H02-1863 (Invited) at 243rd ECS Meeting and SOFC-XVIII 

Boston, MA, May 29 - June 2, 2023

Abstract: In the era of emerging computing paradigms and artificial neural networks, hardware and functionality requirements are in the surge. In order to meet low power and latency criteria, new architectures for in-memory computing are being explored as alternatives to traditional von Neumann machines, which requires technological breakthrough at the semiconductor device level such as vertical gate-all-around junctionless nanowire field effect transistors (VNWFET), that can address many process challenges such as downscaling, short-channel effects, compactness and electrostatic control. Its integration in the mainstream design flow is not straightforward and requires design technology co-optimization (DTCO) at an early stage. This invited paper explores strategies for accurate characterization and parameter extraction of the VNWFETs to feed the DTCO compact models

Fig: Final verification using full 3D multiphysics device thermal simulation, accounting for both ballistic and diffusive heat flux