Showing posts with label EKV model. Show all posts
Showing posts with label EKV model. Show all posts

Sep 29, 2025

[Thesis] Verilog-A MOSFET Model for Analog IC Design

Master Thesis by Alba Gallego Velázquez
Defended: July 1, 2025
Technical University of Crete, Chania
Tutor: Prof. Matthias Bucher

Abstract: The present thesis sets out the development and implementation of a compact model of a MOSFET, based on the theoretical EKV model, and implemented using the Verilog-A language. The utilization of simulation and compilation environments, such as the open server OpenVAF and Ngspice, is instrumental in facilitating the effective execution of the work. The construction of a model that can perform the function of an nMOS or a pMOS nanometric operating in a saturated state is facilitated by these. In this model, physical dependencies and second-order effects are incorporated, ensuring the attainment of continuous expressions for all inversion regions. The model's behavior is validated against experimental data by means of simulation. This results in an accurate, compact and versatile model, which is suitable for supporting integrated analog circuits designs with a wide range of values for the inversion coefficient.
Fig: Normalized (𝐺𝑚𝑠 ·𝑈𝑡)/ID of the nMOS vs. the inversion coefficient (IC)




Aug 31, 2020

[paper] Bulk CMOS Technology at Sub-Kelvin Temperature

Characterization and Modeling of 0.18µm Bulk CMOS Technology 
at Sub-Kelvin Temperature 
Teng-Teng Lu1,2, Zhen Li1,2, Chao Luo1,2, Jun Xu2, Weicheng Kong3
and Guoping Guo1 (Member, IEEE) 
IEEE J-EDS, vol. 8, pp. 897-904, 2020
DOI: 10.1109/JEDS.2020.3015265.

1Key Laboratory of Quantum Information, University of Science and Technology of China, Hefei 230026, China 
2Department of Physics, University of Science and Technology of China, Hefei 230026, China 
3Department of Quantum Hardware, Origin Quantum Computing Company Limited, Hefei 230026, China

Abstract: Previous cryogenic electronics studies are mostly at 77K and 4.2K. Cryogenic characterization of a 0.18μm standard bulk CMOS technology (operating voltages: 1.8V and 5V) is presented in this paper. Several NMOS and PMOS devices with different width to length ratios (W/L) were extensively tested and characterized under various bias conditions at sub-kelvin temperature. In addition to devices dc characteristics, the kink effect and current overshoot phenomenon are observed and discussed at sub-kelvin temperature. Especially, the current overshoot phenomenon in PMOS devices at sub-kelvin temperature is shown for the first time. The transfer characteristics of MOSFET devices (1.8V W/L = 10μm/10μm) at sub-kelvin temperature are modeled using the simplified EKV model. This work facilitates the CMOS circuits design and the integration of CMOS circuits with silicon-based quantum chips at extremely low temperatures.
FIG: IDS-VGS curves of large thin TOX NMOS (a,b,e,f) and PMOS (c,d,g,h) devices at sub-kelvin temperature measured (symbols) and simulated (solid lines). 

Aknowlegement: This work was supported in part by the National Key Research and Development Program of China under Grant 2016YFA0301700, in part by the National Natural Science Foundation of China under Grant 11625419, in part by the Anhui initiative in Quantum information Technologies under Grant AHY080000, and in part by the USTC Center for Micro and Nanoscale Research and Fabrication.

Jun 4, 2020

[paper] Unified Analytical Transregional MOSFET Model

Kalra, S, Bhattacharyya, AB. 
A Unified Analytical Transregional MOSFET Model for Nanoscale CMOS Digital Technologies
Int J Numer Model. 2020; 33:e2700
https://doi.org/10.1002/jnm.2700

Abstract: For IC designers, power has always been the main design constraint. Near threshold (moderate inversion) computing is a promising technique to manage power and energy requirements. A modeling framework specific to moderate inversion is developed in literature known as Transregional Mosfet Model (TRM). This paper presents an extension of TRM model by considering the lateral and vertical field dependent mobility of carriers that make it suitable for circuit design at supply voltages not restricted to near threshold voltage. The model proposed is the unified model applicable in all operating regions (weak, moderate, and strong) and all saturation levels from a long channel with negligible effect of velocity saturation to a short channel having extreme velocity saturation. Further, it has been shown that the proposed drain current model can be reduced to unified interpolated expression of EKV model for long channel MOSFET.

FIG: Comparison of (A) proposed model, (B) weak inversion approximation, (C) strong inversion approximation, with transregional MOSFET model (TRM) and BSIM4 at 22nm technology node.