[mos-ak] [Final Program] Spring MOS-AK Workshop at DATE Conference in Lausanne, March 31, 2017

 Spring MOS-AK Workshop  

   at DATE Conference in Lausanne, March 31, 2017
     Final Program online http://mos-ak.org/lausanne_2017/   

 
 Together with the MOS-AK workshop chair, Dr. Jean-Michel Sallese, EPFL and International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to the Spring MOS-AK Workshop which will be held during DATE Conference on March 31, 2017 in Lausanne (CH). The MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Important Dates:

• Preannouncement - Dec. 2016
  
• Call for Papers - Jan. 2017
  
• Final Workshop Program - Feb. 2017
  
• MOS-AK Workshop - March 31, 2017

Venue:

Swisstech Convention Centre Quartier Nord de l'EPFL Route Louis-Favre 2 CH-1024 Ecublens (CH)

Final Program of Spring MOS-AK/DATE workshop is available online
http://www.mos-ak.org/lausanne_2017/

Online MOS-AK/DATE Workshop Registration

https://www.date-conference.com/registration
(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

WG280217

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[ngspice] FM Bugger Circuit

Project Summary by https://www.eeweb.com
The project circuit design is a FM Bugger circuit. It works like a transmitter that transmits and projects information signals into the air wherein a FM radio will act as a receiver which would receive the transmitted signal. The circuit and the FM radio must be tuned-in with the same frequency to be able to transmit and receive information in the same channel. The FM bugger circuit is originally designed to be used like a spy gadget to eavesdrop other people’s conversations. Though it is designed that way, it is pretty much useful as a transmitter or as a walkie-talkie to relay messages in a distance [read more...]

Testing and Design Procedure
The FM bugger circuit is tested using PartSim and the NGSpice to test the output of the circuit:

FM Bugger Circuit Simulation
R1 Net1009 Mic 22K
R2 Net1009 Net1016 47K
R3 Net1003 0 33K
C1 Net1016 Mic 1NF
C2 Net1016 0 1NF
C3 Net1002 Net1003 4.7pF
C4 Net1002 Antenna 1NF
C5 Net1009 0 22NF
C6 Net1009 Net1002 50pF
L1 Net1009 Net1002 9NH
Q1 Net1002 Net1016 Net1003 2N2222
V1 Net1009 0 3V
V2 Mic 0 SINE ( 1 1 20Khz 0.0S )
R4 0 Antenna 1K
.options rshunt = 1.0e12 KEEPOPINFO
.MODEL 2N2222 NPN IS =3.0611E-14 NF =1.00124
+ BF =220 IKF=0.52 VAF=104 
+ ISE=7.5E-15 NE =1.41 NR =1.005 BR =4 
+ IKR=0.24 VAR=28 ISC=1.06525E-11 NC =1.3728 RB =0.13 
+ RE =0.22 RC =0.12 CJC=9.12E-12 MJC=0.3508 VJC=0.4089 
+ CJE=27.01E-12 TF =0.325E-9 TR =100E-9
.control
OP
write Net1002 Net1003 Net1009 Net1016 Mic Antenna I(V1) I(V2)
set appendwrite true
rusage everything
.endc
.end

Conclusion
The simulation of the FM bugger circuit in PartSim shows that the circuit is working. The microphone was assumed to have an input of a 20 kHz sinusoidal wave. Then, the output signal at the load, R4 assumed to be the antenna for the circuit, turns out to produce a FM signal. Therefore, the FM bugger circuit itself has a great possibility to succeed and operate in real

Project Links:
http://www.schematics.com/embed/fm-bugger-circuit-36638/
http://www.pcbweb.com/projects/DqEwZcNdcy3ddghPnJefdJIzTcWqLd

[paper] Readout electronics for LGAD sensors

Readout electronics for LGAD sensors

O. Alonso,^a N. Franch,^a J. Canals,^a F. Palacio,^a M. López,^a A. Vilà,^a A. Diéguez,^a
M. Carulla,^b D. Flores,^b S. Hidalgo,^b A. Merlos,^b G. Pellegrini^b and D. Quirion^b
aDepartment of Engineering: Section of Electronics, University of Barcelona,
C/ Martí i Franquès nº1, Barcelona, 08028 Spain
^bInstituto de Microelectrónica de Barcelona — Centro Nacional de Microelectrónica (IMB-CNM),
Campus UAB, Cerdanyola del Vallès, Bellaterra, Barcelona, 08193 Spain
doi:10.1088/1748-0221/12/02/C02069

Abstract: In this paper, an ASIC fabricated in 180 nm CMOS technology from AMS with the very front-end electronics used to readout LGAD sensors is presented as well as its experimental results. The front-end has the typical architecture for Si-strip readout, i.e., preamplification stage with a Charge Sensitive Amplifier (CSA) followed by a CR-RC shaper. Both amplifiers are based on a folded cascode structure with a PMOS input transistor and the shaper only uses passive elements for the feedback stage. The CSA has programmable gain and a configurable input stage in order to adapt to the different input capacitance of the LGAD sensors (pixelated, short and long strips) and to the different input signal (depending on the gain of the LGAD). The fabricated prototype has an area of 0.865mm  0.965mm and includes the biasing circuit for the CSA and the shaper, 4 analog channels (CSA+shaper) and programmable charge injection circuits included for testing purposes. A first approach to find the proper dimensioning of the input transistor has been done using a Matlab script, where the transconductance value has been calculated with the EKV model

Acknowledgments This work has been partially funded by the Spanish national projects FPA2013-48387 and FPA2015-71292. In addition, this work has been done in the framework of RD50 CERN collaboration.

1-cent "lab on a chip" could save lives

Rahim Esfandyarpour, Stanford University, helped to develop a way to create a diagnostic "lab on a chip" for just a penny:
"I'm pretty sure it will open a window for researchers because it makes life much easier for them - just print it and use it," said Esfandyarpour. The results of this research were recently published in the journal Proceedings of the National Academy of Sciences [Source: Stanford Medicine]

[paper] Bipolar and MOS Transistors Under the Effect of Radiation

Measurements of the Electrical Characteristics of Bipolar and MOS Transistors

Under the Effect of Radiation

K. O. Petrosyants, L. M. SamburskiiI. A. KharitonovM. V. Kozhukhov

Meas Tech (2017) doi:10.1007/s11018-017-1100-z

ABSTRACT: The specific nature of the process of measuring the electrical characteristics of bipolar and metal-oxidesemiconductor (MOS) transistors subjected to the action of neutron, electron, and gamma irradiation is considered. An automated measurement system is developed. Examples illustrating the use of the system for investigations of the radiation hardness of transistors are presented and the parameters of SPICE models for use in circuit design (including SOI/SOS CMOS circuits with EKV-RAD macromodel) are determined.

Translated from Izmeritel’naya Tekhnika, No. 10, pp. 55–60, September, 2016 [read more...]

[call for papers] 2017 IEEE S3S Conference

Overview: This industry - wide event has gathered, for over 30 years, industry leaders and widely known experts, in a social - oriented environment. Our contributed papers and invited talks are focused on SOI Technology, Low - Voltage Devices/Circuits/Architectures, and 3D Integration. These 3 technologies will play a major role in tomorrow's industry as they enable application - tailored and Energy / Cost efficient circuit designs.

Important Dates

Paper Submission Deadline: May 22, 2017

Acceptance Notification: July 1, 2017

The conference at a glance

Monday to Wednesday, Oct. 16-18, 2017: Technical Sessions

Thursday, Oct.19: Fully - Depleted SOI Circuit Design; Full-day Tutorial
Tuesday, Oct.17: Monolithic 3D Half-day Tutorial

---

Scope: We welcome papers in the following areas:
Silicon On Insulator (SOI)
• Advanced Materials, Substrate and Processes • Device Physics, Characterization and Modeling • Device/Circuit Integration • SOI Design, Circuits and Applications	• Non-Digital Devices and Applications (RF, HV, Photonics, NEMS, MEMS, Analog...) • New SOI Structures, Circuits and Applications
Low-Voltage Microelectronics
• Space-Based and Unattended Remote Sensors • Biomedical Devices • Low-Voltage Handheld/wireless systems • Ultra-Low-Power Digital Computation • Analog and RF Technologies	• Low Voltage Memory Technologies • Energy Harvesting Techniques • Asynchronous Circuits • Novel Device and Fabrication Technology
3D Integration
• Low Thermal Budget Processing • Fabrication Techniques and Bonding Methods • Design and Test Methodologies • Processes for Multi Wafer Stacking • 3D IC EDA and Design Technology	• Heterogeneous Structures • 3D Manufacturing and Logistics • Reliability of 3D Circuits • Fault Tolerant 3D Designs

---

Paper Submission:
Prospective authors should prepare a 2page abstract (follow online guidelines).
Acceptance is based on paper’s technical quality and relevance.

---

Conference manager contact Joyce Lloyd
6930 De Celis Pl., #36
Van Nuys, CA 91406
Tel: +1 818 795 3768
Fax: +1 818 855 8392

HiSIM-HV and HiSIM2 implemented into ngspice

ngspice (Open Source SPICE Circuit Simulator) supports latest versions of HiSIM_HV and HiSIM2 [read more...]
REF: 

[1] HiSIM 2. Y. Z: Surface-Potential-Based RF MOSFET Model for Circuit Simulation

[2] T. Ezaki, D. Navarro, Y. Takeda, N. Sadachika, G. Suzuki, M. Miura-Mattausch, H. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, and S. Miyamoto, “Non-quasi-static Analysis with HiSIM, a Complete Surface-potential-based MOSFET Model”, Proceedings of the 12 th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES’2005), 923-928 (2005.6), Invited Paper

[3] M. Miura-Mattausch, D. Navarro, Y. Takeda, H.J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi and S. Miyamoto, “MOSFET Modeling for RF Circuit Era”, Proceedings of the 11 th International Conference on Mixed Design Mixed Design of Integrat ed Circuits and Systems (MIXDES’2004), 62-66 (2004), Invited Paper

[4] HiSIM_HV Y. Z: Surface-Potential-Based HV/LD_MOSFET Model for Circuit Simulation

[5] Mattausch,  H.J.;  Umeda,  T.;  Kikuchihara,  H.;  Miura-Mattausch,  M.,  "The  HiSIM compact models of high-voltage/power semiconductor devices for circuit simulation," in Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on , vol., no., pp.1-4, 28-31 Oct. 2014
[6] Mattausch,  H.J.;  Miyake,  M.;  Ii zuka,  T.;  Kikuchihara,  H.;  Miura-Mattausch,  M.,  "The Second-Generation  of  HiSIM_HV  Compact  Models  for  High-Voltage  MOSFETs,"  in Electron Devices, IEEE Transactions on , vol.60, no.2, pp.653-661, Feb. 2013

[paper] Model for Organic Thin-Film Transistor

Physically Based Compact Mobility Model for Organic Thin-Film Transistor

T. K. Maiti, L. Chen, H. Zenitani, H. Miyamoto, M. Miura-Mattausch and H. J. Mattausch

in IEEE Transactions on Electron Devices, vol. 63, no. 5, pp. 2057-2065, May 2016.

doi: 10.1109/TED.2016.2540653

Abstract: A physically based compact mobility model for organic thin-film transistors (OTFTs) with an analysis of bias-dependent Fermi-energy (EF) movement in the bandgap (Eg) is presented. Mobility in the localized and extended energy states predicts the drain-current behavior in the weak and strong accumulation operations of OTFTs, respectively. A hopping mobility model as a function of the surface potential is developed to describe the carrier transport through localized energy states located inside Eg. The Poole-Frenkel parallel-field-effect mobility and vertical-field-effect mobility are considered to interpret the bandlike carrier transport in the extended energy states. The parallel field effect on mobility is more pronounced for shorter channel length OTFTs and is considered by developing a channel-length-dependent mobility model. The vertical field effect on mobility is included to account for the effect of mobility on carrier transport at high gate-voltage-induced fields. We also compared the model results with 2-D device simulations and measurements to verify the developed mobility model [read more...]

Workshop on biomedical applications at EPFL Lausanne

Data communication and remote powering for biomedical applications 

Workshop organized by Prof. Catherine Dehollain and Dr. Maria-Alexandra Paun
on February 24, 2017 at 09:00-17:00 in Room BC 01, EPFL Lausanne

Workshop Program

Time	Invited Speaker	Presentation Title
09:00-09:35	Professor Catherine DEHOLLAIN, EPFL, Lausanne, RF IC group	“Remotely powered sensor networks for medical applications”
09:35-10:10	Dr. Maria-Alexandra PAUN, EPFL, Lausanne, RF IC group	“Modeling and analysis of antennas in cochlear implants”
10:10-10:45	Dr. Gürkan YILMAZ, EPFL, Lausanne, RF IC group	“Wireless Power Transfer and Data Communication for Intracranial Neural Implants. Case Study: Epilepsy Monitoring”
Coffee Break (30 minutes)
11:15-11:50	Dr. Mehrdad GHANAD, EPFL, Lausanne, RF IC group	“Remotely-Powered Batteryless Implantable Local Temperature Monitoring System for Freely Moving Mice”
11:50-12:25	Francesca STRADOLINI, EPFL, Lausanne, LSI laboratory	“On-line monitoring of aesthetics during surgery: opportunities and challenges”
12:25-13:00	Professor Adrian M. IONESCU, EPFL, Lausanne, Nanolab laboratory	“Wearable biosensors and their applications in future digital health”
LUNCH (90 minutes)
14:30-15:05	Dr. Wladek GRABINSKI, MOS-AK Association (EU)	“FOSS TCAD/EDA simulation tools with molecular/bio/med modeling examples”
15:05-15:40	Dr. Albrecht LEPPLE-WIENHUES, Valtronic Technologies SA	“Ear infection, drug injectors and blood donation: innovative medical device development”
15:40-16:15	Dr. Qing WANG, CHUV, Lausanne	“Development of a flow-through telemetry implant for monitoring cardiovascular blood pressure in small rodents and human”
16:15-16:50	Professor Philippe RYVLIN, CHUV, Lausanne	“Wearable devices for neurological diseases: Towards more rigorous clinical evaluation”
Concluding remarks (10 minutes)

[paper] RF-MEMS for Future Mobile Applications: Experimental Verification of a Reconfigurable 8-Bit Power Attenuator up to 110 GHz

RF-MEMS for Future Mobile Applications: Experimental Verification of a Reconfigurable 8-Bit Power Attenuator up to 110 GHz
Jacopo Iannacci¹ and Christian Tschoban^2
1Center for Materials and Microsystems - CMM, Fondazione Bruno Kessler , Trento, ITALY
²Fraunhofer Institut für Zuverlässigkeit und Mikrointegration IZM , Berlin, GERMANY
Journal of Micromechanics and Microengineering
Accepted Manuscript online 8 February 2017

Abstract

RF-MEMS technology is indicated as a key enabling solution to realise the high-performance and highly-reconfigurable passive components that future 5G communication standards will demand for. In this work, we present, test and discuss a novel design concept of an 8-bit reconfigurable power attenuator manufactured in the RF-MEMS technology available at the CMM-FBK, in Italy. The device features electrostatically controlled MEMS ohmic switches, in order to select/deselect resistive loads (both in series and shunt configuration) that attenuate the RF signal, and comprises 8 cascaded stages (i.e. 8-bit), thus implementing 256 different network configurations. Fabricated samples are measured (S-parameters) from 10 MHz to 110 GHz in a wide range of different configurations, and modelled/simulated in Ansys HFSS. The device exhibits attenuation levels (S21) in the range from -10 dB to -60 dB, up to 110 GHz. In particular, the S21 shows flatness from 15 dB down to 3-5 dB, from 10 MHz to 50 GHz, while less linear traces up to 110 GHz. Comprehensive discussion is developed around the Voltage Standing Wave Ratio (VSWR), employed as quality indicator for the attenuation levels. Margins of improvement at design level are also discussed, in order to overcome the limitations of the presented RF-MEMS device. The results of S-parameter simulations performed in the Quite Universal Circuit Simulator (QUCS: qucs.sourceforge.net) for a few significant configurations of the RF-MEMS attenuator from 10MHz to 110GHz are reported, too. [read more...]

[SemiWiki] What are the future technology trend for SPICE Modeling?

CEO Interview: Albert Li of Platform Design Automation, Inc (PDA)

/Original material on SemiWiki/

by Daniel Nenni Published on 11-27-2016 02:00 PM

[SemiWiki] What are the future technology trend for SPICE Modeling?

[PDA] Having sufficient data is really the key to the problem, if data is sufficient, model can be automatically generated or synthesized. The concept has already been applied to the case of passive device modeling, such as modeling inductors. EM solvers play the role of proving more “data” or the synthesizers to generate models automatically. We’ve been working with the same concept for the active devices for quite a while, one way is to enable faster measurements, so that a lot more data can be collected and the other way is to achieve huge amount of data based on limited silicon through machine learning, which requires deep understanding of device behaviors, device modeling knowledge, data for the training and years of training experiences, we have already successfully applied the methodologies to our service projects, and tedious tasks such as model re-targeting is now purely done by machines. Machine Learning enabled model targeting from tweaking model parameters to just defining the targets and let the machine finish the job automatically

[SemiWiki] What are other areas in semiconductor you see that Machine Learning can help?

[PDA] We’ve published 3 papers in the past few years related to machine learning, and we used machine-learning algorithms to help on speeding up soft error simulation of logic circuits, automatic statistical modeling, and automatic RF front-end design,so the areas of machine-learning applications are massive. Algorithms, expertise, data and risk are the four key components to access Machine-Learning applications, take device characterization and modeling as examples, we have been working on the machine learning algorithms for over a decade, and we are definitely the experts in device characterization and modeling, we also have huge amount of data and models from previous projects, and these enabled us to train our software or instrument to achieve faster measurements and automatic model generations. 

[Book] Low-power HF Microelectronics: a unified approach

Low-power HF Microelectronics: a unified approach 

ISBN: 9780852968741 e-ISBN: 9781849193610

Editor: Gerson A. S. Machado

Department of Electronic Engineering

Imperial College of Science, Technology and Medicine

London, UK

Front Matter
1 Low-power HF microelectronics: a unified approach
Part 1: Process technology
2 Device structures and device simulation techniques
3 Stanford's ultra-low-power CMOS technology and applications
4 SOI technology
5 Radiation effects on ICs and a mixed analog CMOS-NPN-PJFET-on-insulator technology
Part 2: Device modelling/characterisation and circuit simulation
6 Modelling and characterisation of GaAs devices
7 The EKV Model: a MOST Model Dedicated to Low-Current and Low-Voltage Analogue Circuit Design and Simulation
8 Non-linear dynamic modelling of RF bipolar transistors
9 APLAC - object-oriented circuit simulator and design tool
10 Noise coupling in mixed-signal ASICs
Part 3: Reliability and test
11 Robust design and reliability analysis
12 Dynamic reliability of systems
13 Fault modelling and simulation for the test of integrated analog and mixed-signal circuits
Part 4: Circuit and system design methodology
14 High-speed and low-power techniques in CMOS and BiCMOS
15 Ultra-low-power digital design
16 Matched delay technique for high-speed digital design
17 Statistical design and optimisation for high-yield BiCMOS analog circuits
18 Design considerations for high-speed amplifiers using complementary BJTs
19 S2I techniques for analog sampled-data signal processing
20 Design of wireless portable systems
21 Low-power radio-frequency ICs and system architectures for portable communications
22 Analog and digital CMOS design for spread-spectrum wireless communications
23 Design considerations for BJT active mixers
24 Distortion in short channel FET circuits
25 Intelligent sensor systems and smart sensors: concepts, focus points and technology
26 Intelligent sensor systems and smart sensors: applications
Back Matter

[paper] Semiempirical Modeling of Reset Transitions in Unipolar, Resistive-Switching Based Memristors

Semiempirical Modeling of Reset Transitions in Unipolar Resistive-Switching Based Memristors

Rodrigo Picos, Juan Bautista Roldan, Mohamed Moner Al Chawa, Pedro Garcia-Fernandez, Francisco Jimenez-Molinos, Eugeni Garcia-Moreno 

Radioengineering, 24(2): 420-424 (2015)

We have measured the transition process from the high to low resistivity states, i.e., the reset process of resistive switching based memristors based on Ni/HfO2/Si-n+ structures, and have also developed an analytical model for their electrical characteristics. When the characteristic curves are plotted in the current-voltage (I-V) domain a high variability is observed. In spite of that, when the same curves are plotted in the charge-flux domain (Q-f), they can be described by a simple model containing only three parameters: the charge (Qrst) and the flux (frst) at the reset point, and an exponent, n, relating the charge and the flux before the reset transition. The three parameters can be easily extracted from the Q-f plots. There is a strong correlation between these three parameters, the origin of which is still under study [read more...]

Citation:    
Picos, R.; et al. Semiempirical Modeling of Reset Transitions in Unipolar Resistive-Switching Based Memristors; Radioengineering, 24(2): 420-424 (2015). [http://hdl.handle.net/10481/36994]

[paper] Statistical model of the NBTI-induced ΔVth, ΔSS, and Δgm degradations in advanced pFinFETs

Statistical model of the NBTI induced threshold voltage, subthreshold swing, and transconductance degradations in advanced pFinFETs
J. Franco, B. Kaczer, S. Mukhopadhyay, P. Duhan, P. Weckx, Ph.J. Roussel, T. Chiarella, L.-Å. Ragnarsson, L. Trojman, N. Horiguchi, A. Spessot, D. Linten, A. Mocuta
2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2016, pp. 15.3.1-15.3.4.
DOI: 10.1109/IEDM.2016.7838422

Abstract

We study the stochastic NBTI degradation of pFinFETs, in terms of ΔVth, ΔSS, and Δgm. We extend our Defect-Centric model to describe also the SS distribution in a population of devices of any area, at any stage of product aging. A large fraction of nanoscale devices is found to show a peak g m improvement after stress. We explain this effect in terms of the interaction of individual defects with the percolative channel conduction, and we propose a statistical description of g m aging. Our Vth, SS, and gm aging models are pluggable into reliability-enabled compact models to estimate design margins for a wide variety of circuits. Selected nanoscale device characteristics resulting from 3 percolation paths, generated with the EKV model [read more...]

Publication stats: 1260 Reads

1260 Reads: Open-source circuit simulation tools for RF compact semiconductor device modelling

Article · Sep 2014 · International Journal of Numerical Modelling Electronic Networks Devices and Fields

[paper] Impact of technology scaling on analog and RF performance of SOI–TFET

Impact of technology scaling on analog and RF performance of SOI–TFET

P Kumari, S Dash and G P Mishra
Advances in Natural Sciences: Nanoscience and Nanotechnology, Volume 6, Number 4 

Published 9 October 2015

Abstract

This paper presents both the analytical and simulation study of analog and RF performance for single gate semiconductor on insulator tunnel field effect transistor in an extensive manner. Here 2D drain current model has been developed using initial and final tunneling length of band-to-band process. The investigation is further extended to the quantitative and comprehensive analysis of analog parameters such as surface potential, electric field, tunneling path, and transfer characteristics of the device. The impact of scaling of gate oxide thickness and silicon body thickness on the electrostatic and RF performance of the device is discussed. The analytical model results are validated with TCAD Sentaurus device simulation results [read more...]

Citations
[1] Extensive electrostatic investigation of workfunction-modulated SOI tunnel FETs Subhrasmita Panda et al  2016 Journal of Computational Electronics 15 1326
[2] S. Sahoo et al  2016 337
[3] A comprehensive investigation of silicon film thickness (T SI) of nanoscale DG TFET for low power applications Rajeev Ranjan et al  2016 Advances in Natural Sciences: Nanoscience and Nanotechnology 7 03500
[4] A complete analytical potential based solution for a 4H-SiC MOSFET in nanoscale M K Yadav et al  2016 Advances in Natural Sciences: Nanoscience and Nanotechnology 7 025011
[5] S. Dash et al  2015 447
   

[paper] Processes of AM-PM Distortion in Large-Signal Single-FET Amplifiers

Processes of AM-PM Distortion in Large-Signal Single-FET Amplifiers

S. Golara, S. Moloudi and A. A. Abidi, " 

in IEEE Transactions on Circuits and Systems I: Regular Papers, 

vol. 64, no. 2, pp. 245-260, Feb. 2017; doi: 10.1109/TCSI.2016.2604000

Abstract: Using an appropriate formulation of field-effect transistor (FET) current as a nonlinear function of terminal voltages, and a simplified model of gain compression in common source amplifiers, we are able to identify four principal sources of amplitude-to-phase (AM-PM) distortion. A new analysis shows the varactor effect of gate-source capacitance on AM-PM distortion, and the changing Miller-multiplied gate-drain capacitance as the field-effect transistor (FET) is driven into compression. The phase shift in the load impedance at the frequency of operation and incomplete suppression of 2nd harmonic by a resonant load of limited Q are explained and analyzed. We are able to identify the dominant mechanism of AM-PM distortion in various practical circuits, which then suggests methods of remediation. The analysis was put to test by predicting the measured AM-PM distortion of power amplifiers reported in the literature. Good agreement is found in all cases, with insights gained into the dominant cause of distortion in each case. In this paper, AM-PM distortion is first defined in Section II. In Section III, the EKV model of the MOSFET is briefly presented and dominant mechanisms are explained. In Section IV the analysis is compared against measured data to validate the theory and Section V summarizes the conclusions [read more...]

IEEE Workshop on Compact Modeling

IEEE Workshop on Compact Modeling

March 3, 2017

Technical Sponsorship by: IEEE Electron Devices Society UP Chapter

Organized by: Department of Electrical Engineering, IIT Kanpur

Coordinator: Prof. Yogesh Singh Chauhan

Venue: Outreach Auditorium, IIT Kanpur

IEEE Workshop on Compact Modeling Agenda:

Time	Topic	Speaker
8:00 - 8:15	Workshop inauguration by Director IIT Kanpur and IEEE-UP Chairman
8:15 - 9:00	Industry Standard Compact Modelling	Dr. Yogesh Singh Chauhan IIT Kanpur
9:00 - 9:30	Modelling of mismatch and process variations	Dr. Abhisek Dixit IIT-Delhi
9:30 - 10:00	TBA	Dr. Nihar Ranjan Mohapatra IIT-Gandhinagar
10:00 - 10:30	Modelling of normally-off GaN based MOSHEMT	Dr. Trupti Ranjan Lenka NIT Silchar
10:30 - 10:45	ASM-HEMT: Industry standard compact model for GaN HEMTs	Dr. Sudip Ghosh IIT-Kanpur
10:45 - 11:00	Modelling of quasi ballistic transport in nano-wire transistors	Mr. Avirup Dasgupta IIT Kanpur
11:00 - 11:15	TBA	Mr. Priyank Rastogi IIT Kanpur
11:15 - 11:30	Compact modelling of TMD based thin body transistors	Mr. Chandan Yadav IIT Kanpur
11:30 - 11:45	Tea Break
11:45 - 12:15	Qualification techniques for sim models for EEsof products	Mr. Mohit Khanna Keysight Technologies
12:15 - 12:45	High frequency device characterization and modeling for THz applications	Prof. Thomas Zimmer IMS-BORDEAUX
12:45 - 2:00	Lunch
2:00 - 2:30	Device design consideration: IoT perspective	Dr. Santosh Kumar Vishvakarma IIT-Indore
2:30 - 3:00	TBA	Dr. Aditya Sankar Medury IISER-Bhopal
3:00 - 3:30	Simulations, analysis and applications of doping- and junction- free transistors	Dr. Jawar Singh IIIT-Jabalpur
3:30 - 4:00	Design of radiation hardened 24-bit ADC for generic applications	Mr. H.S.Jattana SCL
4:00 - 4:15	Tea Break
4:15 - 4:45	Role of Feynman diagrams in energy band structure of materials - A post density functional theory approach	Dr. Sitangshu Bhattacharya IIIT-Allahabad
4:45 - 5:15	TBA	Dr. Swaroop Ganguly IIT-Bombay
5:15 - 5:45	TBA	Dr. Saurabh Lodha IIT-Bombay
5:45 - 6:15	TBA	Dr. Udayan Ganguly IIT-Bombay
6:15 - 6:45	TBA	Dr. Manoj Saxena Delhi University
6:45 - 7:00	Closing Keynote

#Memristors, the fourth fundamental circuit element? https://t.co/V03Zp7Oaxw #cad #feedly #papers

#Memristors, the fourth fundamental circuit element? https://t.co/V03Zp7Oaxw #cad #feedly #papers

— Wladek Grabinski (@wladek60) January 31, 2017

from Twitter https://twitter.com/wladek60

January 31, 2017 at 02:53PM
via IFTTT

[chapter] Near-Threshold Digital Circuits for Nearly-Minimum Energy Processing

Near-Threshold Digital Circuits for Nearly-Minimum Energy Processing

Massimo Alioto

Department of Electrical & Computer Engineering, National University of Singapore

in Enabling the Internet of Things; pp 95-148 

DOI: 10.1007/978-3-319-51482-6_4

This chapter addresses the challenges and the opportunities to perform computation with nearly-minimum energy consumption through the adoption of logic circuits operating at near-threshold voltages. Simple models are provided to gain an insight into the fundamental design tradeoffs. A wide set of design techniques is presented to preserve the nearly-minimum energy feature in spite of the fundamental challenges in terms of performance, leakage and variations. Emphasis is given on debunking the incorrect assumptions that stem from traditional low-power common wisdom at above-threshold voltages. The traditional EKV model is very useful for quick estimates, but it oversimplifies the IV characteristics that is observed in actual nanometer CMOS technologies [read more...]

[paper] Electronically tunable MOSFET-based resistor

Electronically tunable MOSFET-based resistor used in a variable gain amplifier or filter

W. L. Tan, C. H. Chang and L. Siek

Nanyang Technological University; Singapore 

2016 International Symposium on Integrated Circuits (ISIC), Singapore, 2016, pp. 1-4.

doi: 10.1109/ISICIR.2016.7829715

Abstract: We present a new design of an electronically tunable linear MOS resistor circuit that operates in the subthreshold saturation region, supported with mathematical derivations and simulation results using CSM0.13µm technology. For a given potential difference across the MOS resistor, its gate voltage will be automatically biased through feedback to provide the correct amount of current based on the desired resistance set through the bias current. Equating the output current of the OTA with the subthreshold equation of the EKV model. In comparison with an existing design, the proposed design offers equal tunabilty with 36 less transistors for unidirectional current and 28 less transistors with one more bias current transistor for bidirectional current. A bias current ranging between 10nA to 100nA offers a tunable linear resistance between 20MΩ to 140MΩ [read more...]

OCS: Octave Circuit Simulator

OCS was developed during the CoMSON (Coupled Multiscale Simulation and Optimization) project which involved several universities but also several industrial partners. Each of the industrial partners at the time was using its own circuit simulation software and each software had different file formats for circuit netlists. Given the purposes of the project and the composition of the consortium the main design objectives for OCS where

• provide a format for "element evaluators" independent of time-stepping algorithms
• provide a "hierarchical" data structure where elements could be composed themselves of lumped-element networks
• allow coupling of lumped-element networks (0D) and 1D/2D/3D device models
• use an intermediate/interchange file format so that none of the formats in use by the industrial partners would be favoured over the others
• be written in an interpreted language for quick prototyping and easy maintenance
• be Free Software

[read more...]

[Course] Advanced CMOS/FinFET Fabrication

February 6, 2017; Portland, OR, USA

Semiconductor and integrated circuit developments continue to proceed at an incredible pace. For example, today’s microprocessor chips have one thousand times the processing power of those a decade ago. These challenges have been accomplished because of the integrated circuit industry’s ability to track something known as Moore’s Law. Moore’s Law states that an integrated circuit’s processing power will double every two years. This has been accomplished by making devices smaller and smaller. The question looming in everyone’s mind is “How far into the future can this continue?” Advanced CMOS/FinFET Fabrication is a 1-day course that offers detailed instruction on the processing used in a modern integrated circuit, and the processing technologies required to make them. We place special emphasis on current issues related to manufacturing the next generation devices. This course is a must for every manager, engineer and technician working in the semiconductor industry, using semiconductor components or supplying tools to the industry.

Register for this Course

SimCAS symbolic analog simulator

Simcas is a simple and very flexible analog simulator. SimCAS uses symbolic equations to define components and solves the net system by using a "Computer Algebra System" algorithm [read more at: SimCAS Web Site]

Related papers:

[1] K. Singhal and J. Vlach, "Symbolic analysis of analog and digital circuits," in IEEE Transactions on Circuits and Systems, vol. 24, no. 11, pp. 598-609, Nov 1977. doi: 10.1109/TCS.1977.1084282

[2] G. M. Wierzba, A. Srivastava, V. Joshi, K. V. Noren and J. A. Svoboda, "Sspice-a symbolic SPICE program for linear active circuits," Proceedings of the 32nd Midwest Symposium on Circuits and Systems,, Champaign, IL, 1989, pp. 1197-1201 vol.2. doi: 10.1109/MWSCAS.1989.102070

[3] G. G. E. Gielen, H. C. C. Walscharts and W. M. C. Sansen, "ISAAC: a symbolic simulator for analog integrated circuits," in IEEE Journal of Solid-State Circuits, vol. 24, no. 6, pp. 1587-1597, Dec 1989. doi: 10.1109/4.44994

[4] Rob A. Rutenbar; Georges G. E. Gielen; Brian A. Antao, Interactive AC Modeling and Characterization of Analog Circuits via Symbolic Analysis; Computer-Aided Design of Analog Integrated Circuits and Systems; Year: 2002; Pages: 287 - 312, DOI: 10.1109/9780470544310.ch23

[5] G. Fontana; F. Grasso; A. Luchetta; S. Manetti; M. C. Piccirilli; A. Reatti; A new simulation program for analog circuits using symbolic analysis techniques; 2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD); Year: 2015; Pages: 1 - 4, DOI: 10.1109/SMACD.2015.7301682

[paper] 400 fJ Per-Cycle Frequency Reference for IoT

A 400 fJ Per-Cycle Frequency Reference for Internet of Things

Mathieu Coustans, François Krummenacher, Christian Terrier and Maher Kayal

IEL, École Polytechnique Fédérale de Lausanne, Switzerland

Abstract—This work presents an ultra-low power oscillator designed to target different contexts, such as crystal-assisted time keeping, reference oscillator to optimize the always on domain of a microcontroller or wake-up timer. This oscillator enables ultra-low power operation in 180nm CMOS technology with EKV3 compact model; the core oscillator consumes 2.5 nW at room temperature, with a temperature stability of 14 ppm/°C [-40°C - 60°C] and 0.07 %/V supply sensitivity [read more...]

Changing Direction In Chip Design https://t.co/XV84VQnO71 #semi #feedly #papers

Changing Direction In Chip Design https://t.co/XV84VQnO71 #semi #feedly #papers

— Wladek Grabinski (@wladek60) January 26, 2017

Andrzej Strojwas, chief technologist at PDF Solutions and professor of electrical and computer engineering at Carnegie Mellon University—and the winner of this year’s Phil Kaufman Award for distinguished contributions to EDA—sat down with Semiconductor Engineering to talk about device scaling, why the semiconductor industry will begin to fragment around new architectures and packaging, and where are the holes that need to be filled.

from Twitter https://twitter.com/wladek60

January 26, 2017 at 08:12PM
via IFTTT

[EUROSOI ULIS] Deadline for abstract submission extended to January 29, 2017

Submit your abstract for  Conference to be held in Athens in April 2017 as soon as possible. We would like to inform you that, due to several requests, the deadline for abstract submission has been extended to January 29, 2017, Please note that there will be both Oral and Poster Sessions 

Call for Papers

The organizing committee invites scientists and engineers working in the above fields to actively participate by submitting high quality papers. Original 2-page abstracts with illustrations will be accepted for review in pdf format. The accepted abstracts will be published in a Proceedings book with an ISBN. A 4-page follow-up paper delivered before will be published in IEEE Xplore Digital Library. The authors of the best papers will be invited to submit a longer version for publication in a special issue of Solid-State Electronics. A best paper award will be attributed to the best paper by the SINANO Institute. Both an Oral and a A Poster Session will be organized.

INVITED SPEAKERS

Prof. Maryline Bawedin, IMEP - INP Grenoble MINATEC, "The mystery of the Z2-FET 1T-DRAM memory"

Dr. Frank Schwierz, University of Ilmenau, "The Prospects of 2D Materials for Ultimately-Scaled CMOS"

Dr. Cosmin Roman, ETH Zurich, "Micro and Nano transducers for autonomous sensing applications"

Dr. Carlo Cagli,  CEA-LETI,  "Memories"

Dr. Anda Mocuta, IMEC, "Nanoscale FET"

The EUROSOI ULIS Conference Chairperson: 

Prof. Androula G. Nassiopoulou

NCSR Demokritos 

Institute of Nanoscience and Nanotechnology, 

Athens, Greece 

#TCAD Simulation of #Organic #Optoelectronic #Devices https://t.co/k7iZDQjppR #papers

#TCAD Simulation of #Organic #Optoelectronic #Devices https://t.co/k7iZDQjppR #papers

— Wladek Grabinski (@wladek60) January 23, 2017

from Twitter https://twitter.com/wladek60

January 23, 2017 at 09:47AM
via IFTTT

2016 Phil Kaufman Award Recipient: Dr. Andrzej Strojwas

Kaufman Award Dinner: Why you should Attend

IEEE’s CEDA and the ESD Alliance – with help from their friends at PDF Solutions, Cadence, Mentor, Synopsys and ACM SIGDA – will host a dinner on Thursday, January 26th, in honor of the 2016 Phil Kaufman Award recipient: Dr. Andrzej Strojwas, Keithley Professor of ECE at Carnegie Mellon and long-time CTO at PDF Solutions.

This year’s Kaufman Award Dinner promises to be an inspiring evening, one that will help you remember why you went to work here in the first place [read more...]

If you want to attend, you can register here.

[mos-ak] [2nd Announcement and Call for Papers] Spring MOS-AK Workshop at DATE Conference in Lausanne, March 31, 2017

 Spring MOS-AK Workshop  

   at DATE Conference in Lausanne, March 31, 2017
     2nd Announcement and Call for Papers   

 
 Together with the MOS-AK workshop chair, Dr. Jean-Michel Sallese, EPFL and International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to the Spring MOS-AK Workshop which will be held during DATE Conference on March 31, 2017 in Lausanne (CH). Planned MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Important Dates:

• Preannouncement - Dec. 2016
  
• Call for Papers - Jan. 2017
  
• Final Workshop Program - Feb. 2017
  
• MOS-AK Workshop - March 31, 2017

Venue:

Swisstech Convention Centre Quartier Nord de l'EPFL Route Louis-Favre 2 CH-1024 Ecublens (CH)

Topics to be covered include the following among other related to the compact/SPICE modeling :

• Compact Modeling (CM) of the electron devices
  
• Advances in semiconductor technologies and processing
  
• Verilog-A language for CM standardization
  
• New CM techniques and extraction software
  
• Open Source TCAD/EDA modeling and simulation
  
• CM of passive, active, sensors and actuators
  
• Emerging Devices, TFT, CMOS and SOI-based memory cells
  
• Microwave, RF device modeling, high voltage device modeling
  
• Nanoscale CMOS devices and circuits
  
• Technology R&D, DFY, DFT and reliability/ageing IC Designs
  
• Foundry/Fabless Interface Strategies
  

Online MOS-AK Abstract Submission:
Prospective authors should submit abstract online 

http://www.mos-ak.org/lausanne_2017/abstracts.php

(any related inquiries can be sent to abstrscts@mos-ak.org)

Online Workshop Registration (to be open Feb.2017):

http://www.mos-ak.org/lausanne_2017 
(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

WG17012017

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[mos-ak] [press note] 9th International MOS-AK Workshop at UC Berkeley, Dec.7, 2016

Arbeitskreis Modellierung von Systemen und Parameterextraktion 

Modeling of Systems and Parameter Extraction Working Group

9th International MOS-AK Workshop

(co-located with the CMC Meeting and IEDM Conference)

December 7, 2016 Berkeley

The MOS-AK Association, a global compact/SPICE modeling and Verilog-A standardization forum, held its annual Q4 event on December 7, 2016 UC Berkeley as its 9th consecutive International MOS-AK Workshop. The event was coordinated by Larry Nagel, OEC (USA) and Andrei Vladimirescu, UCB (USA); ISEP (FR) representing the International MOS-AK Board of R&D Advisers. The workshop was hosted by Prof. Jaijeet Roychowdhury of EECS at the University of California at Berkeley and co-sponsored by Keysight Technologies and NEEDS of nanoHUB.org.

The workshop provided presentations from the leading developers of compact device models. The audience spanned the full range of the semiconductor industry, including representatives from foundries, model characterization services firms, academic researchers investigating emerging device technologies, and design companies. The amount and breadth of technical information discussed was vast -- here are but a few highlights by ChipGuy:
<https://www.semiwiki.com/forum/content/6542-its-all-about-models.html>

These were but a few of the technical highlights and achievements discussed at the workshop which are available online:
<http://www.mos-ak.org/berkeley_2016>

The MOS-AK Modeling Working Group has various deliverables and initiatives, including: a book entitled "Open Source CAD Tools for Compact Modeling" <www.mos-ak.org/books>; an open Verilog-A directory with compact models <http://www.mos-ak.org/open_dir/>; and supporting FOSS TCAD/CAD software.

The MOS-AK Association plans to continue its standardization efforts by organizing additional compact modeling meetings, workshops and courses in Europe, USA, India and China throughout 2017 year, including:

• Spring MOS-AK Workshop in Lausanne at DATE Conference (March 31 2017) 
  <http://www.mos-ak.org/lausanne_2017>
  
• 2nd Sino MOS-AK Workshop in Hangzhou (June 2017) 
  <http://www.mos-ak.org/hangzhou_2017>
  
• 15th MOS-AK ESSDERC/ESSCIRC Workshop in Leuven (Sept.11, 2017) 
  <http://www.mos-ak.org/leuven_2017>

If you are involved in developing or supporting device models for circuit designers, we would encourage you to become an active participant in the MOS-AK community.

About MOS-AK Association:
MOS-AK, an international compact modeling association primarily focused in Europe, to enable international compact modeling R&D exchange in the North/Latin Americas, EMEA and Asia/Pacific Regions. The MOS-AK Modeling Working Group plays a central role in developing a common language among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact/SPICE modeling and its Verilog-A standardization and related CAD/EDA tools for the compact models development, validation/implementation and distribution.

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[paper] Radiation-Induced Fault Simulation of SOI/SOS CMOS LSI’s Using Universal Rad-SPICE MOSFET Model

Radiation-Induced Fault Simulation of SOI/SOS CMOS LSI’s 

Using Universal Rad-SPICE MOSFET Model

Konstantin O. Petrosyants, Lev M. Sambursky, Igor A. Kharitonov, Boris G. Lvov

J Electron Test (2017)

doi:10.1007/s10836-016-5635-8

Abstract: The methodology of modeling and simulation of environmentally induced faults in radiation hardened SOI/SOS CMOS IC’s is presented. It is realized at three levels: CMOS devices – typical analog or digital circuit fragments – complete IC’s. For this purpose, a universal compact SOI/SOS MOSFET model for SPICE simulation software with account for TID, dose rate and single event effects is developed. The model parameters extraction procedure is described in great depth taking into consideration radiation effects and peculiarities of novel radiation-hardened (RH) SOI/SOS MOS structures. Examples of radiation-induced fault simulation in analog and digital SOI/SOS CMOS LSI’s are presented for different types of radiation influence. The simulation results show the difference with experimental data not larger than 10–20% for all types of radiation.

The electrical schematics of SOS CMOS opamp and 4-bit counter are presented; two variants of either macromodel were used for body-tied partially-depleted transistors: a) core EKV-SOI/ BSIMSOI model; b) EKV-RAD/ BSIMSOI-RAD macromodel. [read more...]

ICMTS 2017 in Grenoble (F)

30th International Conference on Microelectronic Test Structures 

March 27-30, 2017, MINATEC, Grenoble (F)

• Monday 27th March
• Tutorials
• Welcome Reception
• Tuesday 28th March
• SESSION 1: Novel Test Structure
• SESSION 2: Novel Materials
• SESSION 3: Variability
• SESSION Exhibitions
• Wednesday 29th March
• SESSION 4: Device Modeling
• SESSION 5: RF and HV
• SESSION 6: Device Testing
• SESSION 7: Sensor Test Structures
• Thursday 30th March
• SESSION 8: Low Frequency Noise
• SESSION 9: Advanced Test Methods

[read more...]

[paper] Modeling, simulation and implementation of circuit elements in an open-source tool set on the FPAA

Modeling, simulation and implementation of circuit elements in an open-source tool set on the FPAA

Aishwarya Natarajan and Jennifer Hasler

Georgia Institute of Technology Atlanta USA

Analog Integr Circ Sig Process (2017), pp 1–12

doi:10.1007/s10470-016-0914-y

ABSTRACT: An open-source simulator to design and implement circuits and systems, replicating the results from the Field Programmable Analog Array (FPAA) is presented here. The fundamental components like the transistors, amplifiers and floating gate devices have been modeled based on the EKV model with minimal parameters. Systems including continuous-time filters and the analog front-end of a speech processing system have been built from these basic components and the simulation results and the data from the FPAA are shown. The simulated results are in close agreement to the experimental measurements obtained from the same circuits compiled on the FPAA fabricated in a 350 nm process [read more...]

On Layout Tools and others

A while ago SolvEx Group has posted a blog note on the Layout Tools, including the open source ones, too. There are also a few questions which are worth to review again:

1. How is Layout different from Placement and Route?
2. What is the difference between Synopsys Astro and Cadence Virtuoso-do they offer layout or are just placement and routing tools? (Comparing them with Magic and LASI)!
3. What is the intermediate map/snapshot/diagram - which we can use and create a complete chip out of? For example after seeing the Chip and reverse engineering the same- what is that something which I can use to create my own chip in the foundry? Reference - Chinese Mobile chips. They do the same-as they bypass the flow for design entry/verification/simulation/floor planning etc and release the chip within a few hrs of seeing the original chip(say famous case of duplicating iPhone/Nokia in the Chinese markets)
4. Are Stick Diagrams passed to the Foundry or else what is the base unit that is given to Foundry as an input to be manufactured as a chip.
5. Giving below a collection all possibly available Layout Tools (Categorized as Open Source, Cheap, Expensive)

Open source software	Description	Web site
wol	Wol is a graphical environment for IC mask layout	http://www.cs.berkeley.edu/~lazzaro/chipmunk/describe/wol.html
toped	Micron based layout editor with extensive scripting capabilities. Under active development and part of Fedora Electronic Lab.	http://www.toped.org.uk
microwind3	Lambda based layout editor especially adapted for interactive design with Spice. This used to be completely free, but now only a Lite version is.	http://www.microwind.org
magic	Lambda based layout editor with good options for writing CIF and/or GDS files. Supports scripting. Large user base. Part of Fedora Electronic Lab. Used for extraction and CIF/GDS creation by the pharosc libraries	http://opencircuitdesign.com/magic
lasi	LASI stands for LAyout Software for Individuals. It is designed to run on Windows, though it also runs on Linux under Crossover Office. Actively used software with frequent updates.	http://lasihomesite.com
kic	Part of open source packages released by Whiteley Research.	http://wrcad.com/freestuff.html
graal	Lambda based layout editor allowing conversion to CIF and GDS with appropriate technology files. Dreal is the companion software to view CIF and GDS. Part of a tool set from Alliance which is probably the best open-source software for IC design. Comes with own standard cell library. Part of Fedora Electronic Lab. The pharosc standard cells are drawn with graal.	http://www-asim.lip6.fr/recherche/alliance
electric	Comprehensive set of software programs designed around the concept of silicon compilation. Version 6 crashed a lot, and stored all design data in a single file which exposed one to the risk of file corruption and loss of all data (I speak from experience). New version written in Java. Extensive documentation.	http://www.staticfreesoft.com/productsSoftware.html
dreal	Simple layout editor which uses CIF or GDS as its native format. Companion software is Graal.	http://www-asim.lip6.fr/recherche/alliance
Cheap software
xic	Whiteley Research Inc. Layout editor with linked Spice simulator. List price is $1195.	http://www.wrcad.com/xic.html
slam-edit	Stabie-Soft Inc. Unix/Linux based layout editor. It seems a licence cannot be purchsed, only leased for one year periods (bad if the company folds). List price on web site is $2,000 per year.	http://www.stabie-soft.com/sledit.html
ledit	Tanner Research Inc. Windows only layout editor popular with mixed signal designers. Ledit sed to cost $1,000, but this price could not be verified (which is surprising since low price is a key selling point of the software).	http://www.tanner.com/EDA/product/Tools_PhysicalLayout.html
layedpro	Mycad Inc. Windows only layout editor designed in Korea but supported for English language users from California. No new product since 2005 on US site, but Korean site seems active. No price could be confirmed.	http://www.mycad.com/02pro/01.html http://www.mycad.co.kr
layed	Catena Software GmbH. Demo versions for Linux and Windows can be downloaded. List price of the basic editor might be €1,585 (could not be recently verified).	http://www.catena-ffo.de/laytools.htm
iced	IC Editors Inc. Windows only editor that used to cost $2,750. Now it is free but with a restrictive licence. Work is on-going to open source it which might make it available under Linux (although the Windows drawing primitives would need to be replaced with GTK).	http://www.iceditors.com
Expensive software
virtuoso	Cadence Design Systems, Inc. The market leader. The price might be $40,000 to lease for one year.	http://www.cadence.com/products/custom_ic/veditor/index.aspx
max	Micro Magic Inc. Looks like a commercial version of Magic. Price is $30,000 for a one year licence. Despite the fancy price tag, something was freely downloadable from the web in the 2004 timeframe.	http://www.micromagic.com
laker	Silicon Canvas Inc. Linux and Unix based editor. Top of the line laker-ddl is $70,000 for a one year licence. Regular Laker 3 is $35,000 for a one year licence.	http://www.sicanvas.com
icstation	Mentor Graphics Corp. No public pricing information could be found.	http://www.mentor.com/cicd/icstation.html