Monday, 27 February 2017

[paper] Readout electronics for LGAD sensors

Readout electronics for LGAD sensors
O. Alonso,a N. Franch,a J. Canals,a F. Palacio,a M. López,a A. Vilà,a A. Diéguez,a
M. Carulla,b D. Flores,b S. Hidalgo,b A. Merlos,b G. Pellegrinib and D. Quirionb
aDepartment of Engineering: Section of Electronics, University of Barcelona,
C/ Martí i Franquès nº1, Barcelona, 08028 Spain
bInstituto de Microelectrónica de Barcelona — Centro Nacional de Microelectrónica (IMB-CNM),
Campus UAB, Cerdanyola del Vallès, Bellaterra, Barcelona, 08193 Spain
doi:10.1088/1748-0221/12/02/C02069

Abstract: In this paper, an ASIC fabricated in 180 nm CMOS technology from AMS with the very front-end electronics used to readout LGAD sensors is presented as well as its experimental results. The front-end has the typical architecture for Si-strip readout, i.e., preamplification stage with a Charge Sensitive Amplifier (CSA) followed by a CR-RC shaper. Both amplifiers are based on a folded cascode structure with a PMOS input transistor and the shaper only uses passive elements for the feedback stage. The CSA has programmable gain and a configurable input stage in order to adapt to the different input capacitance of the LGAD sensors (pixelated, short and long strips) and to the different input signal (depending on the gain of the LGAD). The fabricated prototype has an area of 0.865mm  0.965mm and includes the biasing circuit for the CSA and the shaper, 4 analog channels (CSA+shaper) and programmable charge injection circuits included for testing purposes. A first approach to find the proper dimensioning of the input transistor has been done using a Matlab script, where the transconductance value has been calculated with the EKV model

Acknowledgments This work has been partially funded by the Spanish national projects FPA2013-48387 and FPA2015-71292. In addition, this work has been done in the framework of RD50 CERN collaboration.

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