[paper] A Compact Model for SiC Schottky Barrier Diodes Based on the Fundamental Current Mechanisms

J. R. Nicholls and S. Dimitrijev

Queensland Micro- and Nanotechnology Centre

School of Engineering and Built Environment

Griffith University, Brisbane, QLD 4111, Australia

A Compact Model for SiC Schottky Barrier Diodes Based on the Fundamental Current Mechanisms

IEEE Journal of the Electron Devices Society

doi: 10.1109/JEDS.2020.2991121.

Abstract - We develop a complete compact model to describe the forward current, reverse current, and capacitance of SiC Schottky barrier diodes. The model is based on the fundamental current mechanisms of thermionic emission and tunneling, and is usable over a large range of voltages, temperatures, and for a large range of device parameters. We also demonstrate good agreement with measured data. Furthermore, the development of this model outlines a methodology for transforming a tunneling equation into a compact form without numerical integration-this methodology can potentially be applied to other device structures.

Fig: (a) Structure of a Schottky barrier diode. (b) Equivalent circuit of a Schottky barrier diode, consisting of two current sources (for the forward and reverse bias currents), a shunt capacitance and a series resistance

Acknowledgement - This work was performed at the Queensland Microtechnology Facility (Griffith University), part of the Queensland node of the Australian National Fabrication Facility (ANFF), a company established under the National Collaboration Research Infrastructure Strategy to provide nanofabrication and microfabrication facilities to Australia’s researchers. 

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9081977&isnumber=6423298

[paper] Two Transistors Voltage-Measurement-Based Test Structure for Fast MOSFET Device Mismatch Characterization

J. P. M. Brito and S. Bampi

Two Transistors Voltage-Measurement-Based Test Structure 

for Fast MOSFET Device Mismatch Characterization

IEEE Transactions on Semiconductor Manufacturing

doi: 10.1109/TSM.2020.2988095

Abstract - This work presents a test structure targeted to measure MOSFET mismatches with a fast method. It relies on two single-spot voltage measurements in order to extract VTH and β/β separately. The new methodology gives a theoretical increase in the measurement speed of 30x (23.17x in practice). The coefficient of determination (R2) of the linear regression analysis is used to compare standalone transistor measurements against the new proposed methodology. The correlation in the data demonstrates values not less than 0.94 (R2≥ 0.94). The test structure can reproduce parameter correlations, and it is capable of extracting MOSFET mismatch design parameters, such as Pelgrom’s AVTH, with an error of 2% and Aβ, with a negligible error. The experimental data presented herein are taken from measurements in prototypes fabricated in a 65nm CMOS bulk process. The whole circuit is composed of 16 2D addressable DUT device matrices, each having 256 same-size closely-placed MOSFET devices, totaling 4,096 MOS devices used in single-type (NMOS) transistor array. 

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9068274&isnumber=5159394

[paper] reached 2000 reads at ResearchGate

Grabiński, Władysław, Daniel Tomaszewski, Laurent Lemaitre, and Andrzej Jakubowski

Standardization of the compact model coding: non-fully depleted SOI MOSFET example

Journal of Telecommunications and Information Technology (2005): 135-141.

Abstract - The initiative to standardize compact (SPICE-like) modelling has recently gained momentum in the semiconduc-tor industry. Some of the important issues of the compact modelling must be addressed, such as accuracy, testing, avail-ability, version control, verification and validation. Most com-pact models developed in the past did not account for these key issues which are of highest importance when introducing a new compact model to the semiconductor industry in par-ticular going beyond the ITRS roadmap technological 100 nm node. An important application for non-fully depleted SOI technology is high performance microprocessors, other high speed logic chips, as well as analogue RF circuits. The IC de-sign process requires a compact model that describes in detail the electrical characteristics of SOI MOSFET transistors. In this paper a non-fully depleted SOI MOSFET model and its Verilog-AMS description will be presented. 

Fig: Approximation of the distribution of currents components

in the non-fully depleted SOI MOSFET.  

Keywords: Verilog-AMS, compact model coding, SOI MOSFET.

References:

1. ITRS Roadmap Update, 2003, http://www.public.itrs.net
2. Open Verilog International, "Verilog-AMS, Language Reference Manual", Version 1.9, 1999, http://www.accellera.org/
3. D. Tomaszewski, "Consistent DC and AC models of non-fully depleted SOI MOSFETS in strong inversion", in Proc. 9th Int. Conf. Mix.-Sig. Des. Integr. Cir. Syst. MIXDES, Wrocław, Poland, 2002, pp. 111-114.
4. L. Lemaitre, C. McAndrew, and S. Hamm, "ADMS - automatic device model synthesizer", in Proc. IEEE CICC 2002, Florida, USA, 2002, pp. 27-30.
5. J. R. Hauser, "Small signal properties of field effect devices", IEEE Trans. Electron Dev., vol. 12, pp. 605-618, 1965.
6. D. Tomaszewski, "A small-signal model of SOI MOSFETs capacitances". Ph.D. thesis, Institute of Electron Technology, Warsaw, 1998.
7. L. Lemaitre, W. Grabiński, and C. McAndrew, "Compact device modeling using Verilog-A and ADMS", in Proc. 9th Int. Conf. Mix.-Sig. Des. Integr. Cir. Syst. MIXDES, Wrocław, Poland, 2002, pp. 59-62.
8. C. Lallement, F. Pecheux, and W. Grabiński, "High level description of thermodynamical effects in the EKV 2.6 most model", in Proc. 9th Int. Conf. Mix.-Sig. Des. Integr. Cir. Syst. MIXDES, Wrocław, Poland, 2002, pp. 45-50.

[paper] Memory Technology – A Primer for Material Scientists.

Schenk, Tony, Milan Pesic, Stefan Slesazeck, Uwe Schroeder, and Thomas Mikolajick

Memory Technology–A Primer for Material Scientists

Reports on Progress in Physics (2020)

Abstract - From our own experience in the group, we know that there is quite a gap to bridge between scientists focused on basic material research and their counterparts in a close-to-application community focused on identifying and solving final technological and engineering challenges. In this review, we try to provide an easy-to-grasp introduction to the field of memory technology for materials scientists. As an understanding of the big picture is vital, we first provide an overview about the development and architecture of memories as part of a computer and point out some basic limitations that all memories are subject to. As any new technology has to compete with mature existing solutions on the market, today's mainstream memories are explained and the need for future solutions is highlighted. The most prominent contenders in the field of emerging memories are introduced and major challenges on their way to commercialization are elucidated. Based on these discussions, we derive some predictions for the memory market to conclude the paper.

TABLE OF CONTENTS

1. INTRODUCTION
2. OVERVIEW AND BASIC LIMITATIONS
3. COMMERCIALLY AVAILABLE MAINSTREAM MEMORIES

3.1. Static and Dynamic Random Access Memory (SRAM/DRAM)
3.2. Flash Memory and Solid-State Drive (SSD)
3.3. Magnetic Hard Disk Drives (HDD) and Magnetic Tapes
3.4. Outlook: Market Trends and Drivers

4. EMERGING MEMORIES

4.1. Resistance-based Read-out: Memory Concepts and Basic Considerations
4.2. Anion migration or valence change memory (VCM)
4.3. Cation migration or electrochemical metallization memory (ECM)
4.4. Phase change memory (PCM)
4.5. Magnetoresistive memory (MRM)
4.6. Ferroelectric Memory (FEM)
4.7. Miscellaneous

5. SUMMARY AND CONCLUSION

FIG: Evolution of the mainstream solutions for the respective memories classes. The introduction of Flash memory partially bridged a technology gap around the year 2009. Today, two types of so-called storage-class memories – a memory-type SCM (SCM 1) and a storage-type SCM (SCM 2) – were proposed to overcome the memory gap. NAND flash already fulfills the role of a mainstream SCM 2. For SCM 1, 3D XPoint could be a promising candidate, but is not a dominant mainstream memory. In future, we will likely see different types of SCMs and NV-RAM with different specifications as required by the respective application – because in the end, the overall system cost decides about the choice of the memory.

[paper] Benchmark Tests for MOSFET Thermal Noise Models

Scholten A.J., Smit G.D.J., Pijper R.M.T., Tiemeijer L.F.

Benchmark Tests for MOSFET Thermal Noise Models

In: Grasser T. (eds) Noise in Nanoscale Semiconductor Devices. Springer, Cham

Abstract - In today’s semiconductor industry, many traditional integrated device manufacturers (IDMs) are moving away from chip manufacturing, and transforming into fabless companies that use foundry services for manufacturing their ICs. This is especially true in the field of advanced CMOS technologies. In these companies-under-transformation, the work of the modeling engineer is changing: instead of building models from scratch themselves, most companies choose to use the modeling packages that are delivered by the foundries. There are two reasons to be skeptical about RF noise models. First, measurement of noise, and RF noise in particular, is a difficult and specialist topic. One should not take for granted that every company has the required expertise to carry out this task successfully. A second reason to check RF noise models is that the most popular compact MOSFET models are BSIM4 [1] and BSIMBULK [2], which are not particularly strong and certainly not predictive when it comes to RF noise. As a consequence, the work of the modeling engineer is changing from model creation to model verification.

Tab: Overview of benchmark tests for thermal noise

#No	Bias	Length	Quantity	Test	Remark
#1	VDS = 0V	All	SID	γ = 1
#2	VDS = 0 V	All	SIG	β = 5/12
#3	VDS = 0 V	All	c	c = 0	In the limit f ↓ 0 Hz
#4	Weak Inv	All	SID	F = 1	Disregard SIG contributions from gate to drain
#5	Saturation	Long	SID	γ = 2/3
#6	Saturation	Long	SIG	β = 4/3
#7	Saturation	Long	c	c = 0.4j
#8	Saturation	Short	SID	γ enhancement	Switch off gate resistance
#9	Saturation	All	SID	γ D,NMOS ≥ γ D,PMOS	Switch off gate resistance
#10	Saturation	All	SID	Different Vth flavors should nearly coincide	When plotted against ID

First Online: 27 April 2020

DOI: 10.1007/978-3-030-37500-3_20

Ref: 

[1] N. Paydavosi, T.H. Morshed, D.D. Lu, W. Yang, M.V. Dunga, X. Xi, J. He, W. Liu, K.M. Cao, X. Jin, J.J. Ou, M. Chan, A.M. Niknejad, C. Hu, BSIM4v4.8.0 MOSFET Model - User’s Manual. [Online]. Available: http://bsim.berkeley.edu/models/bsim4/

[2] H. Agarwal, C. Gupta, H.-L. Chang, S. Khandelwal, J.P. Duarte, Y.S. Chauhan, S. Salahuddin, C. Hu, BSIM-BULK106.2.0 MOSFET Compact Model - Technical Manual. [Online]. Available: http://bsim.berkeley.edu/models/bsimbulk/

[paper] DHBT with Record ft of 813 GHz

Y. Shiratori, T. Hoshi and H. Matsuzaki,

InGaP/GaAsSb/InGaAsSb/InP Double Heterojunction Bipolar Transistors

With Record ft of 813 GHz

IEEE EDL vol. 41, no. 5, pp. 697-700, May 2020

doi: 10.1109/LED.2020.2982497

Abstract - We fabricated InGaP/GaAsSb/InGaAsSb/InP double heterojunction bipolar transistors (DHBTs) with an aggressive lateral and vertical scaling technology to improve the current gain cutoff frequency (f_T) further. A 13-nm-thick GaAsSb/InGaAsSb base and a 40-nm-thick InP collector are used to reduce electron transit time. In addition, the width of the base electrode on each side of the emitter is reduced to about 0.05µm to suppress increases in parasitic collector capacitance. A fabricated DHBT with the emitter size of 0.24µm×7.8 µm exhibits maximum differential current gain of ∼95 and collector-emitter breakdown voltage of 2.6V. At a collector current density of 18 mA/µm², the DHBT exhibits f_T of 813 GHz, which is the highest among all types of transistors measured at a room temperature.

Fig: (a) Current gain ( |h21| ) and Mason’s unilateral power gain (Ug ) of the DHBT as a function of frequency. JC and VCE are 18 mA/μm2 and 1.0 V, respectively. ft and fmax are extrapolated by single-pole fitting. Inset: frequency dependence of extrapolating ft and fmax . (b) Gummel’s ft extraction (imaginary part of 1/h21 as a function of frequency). The red circles and black line show experimental data and a linear fitting, respectively.

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9044299&isnumber=9079222

[paper] Physical Mechanisms of Reverse DIBL and NDR in FeFETs With Steep Subthreshold Swing

C. Jin, T. Saraya, T. Hiramoto and M. Kobayashi,

in IEEE J-EDS, vol. 8, pp. 429-434, 2020

doi: 10.1109/JEDS.2020.2986345

Abstract - We have investigated transient IdVg and IdVd characteristics of ferroelectric field-effect transistor (FeFET) by simulation with ferroelectric model considering polarization switching dynamics. We show transient negative capacitance (TNC) with polarization reversal and depolarization effect can result in sub-60mV/dec subthreshold swing (SS), reverse drain-induced barrier lowering (R-DIBL), and negative differential resistance (NDR) without traversing the quasi-static negative capacitance (QSNC) region of the S-shaped polarization-voltage (PV) predicted by single-domain Landau theory. Moreover, the mechanisms of R-DIBL and NDR based on the TNC theory are discussed in detail. The results demonstrated in this work can be a possible explanation for the mechanism of previously reported negative capacitance field-effect transistor (NCFET) with sub-60mV/dec SS, R-DIBL, and NDR.

Equivalent circuits of a ferroelectric capacitor in both static and transient conditions.

#paper: W. E. Muhea, G. U. Castillo, H. C. Ordoñez, T. Gneiting, G. Ghibaudo and B. Iñiguez, "Parameter Extraction and Compact Modeling of 1/f Noise for Amorphous ESL IGZO TFTs," in IEEE J-EDS, vol. 8, pp. 407-412, 2020. https://t.co/SCTs7BsGJZ https://t.co/gZcCgMrYVd

#paper: W. E. Muhea, G. U. Castillo, H. C. Ordoñez, T. Gneiting, G. Ghibaudo and B. Iñiguez, "Parameter Extraction and Compact Modeling of 1/f Noise for Amorphous ESL IGZO TFTs," in IEEE J-EDS, vol. 8, pp. 407-412, 2020. https://t.co/SCTs7BsGJZ

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#paper: J. Leise et al., "Charge-Based Compact Modeling of Capacitances in Staggered Multi-Finger OTFTs," in IEEE J-EDS, vol. 8, pp. 396-406, 2020. https://t.co/zk4BAp2tMj https://t.co/Ay502xHy1w

#paper: J. Leise et al., "Charge-Based Compact Modeling of Capacitances in Staggered Multi-Finger OTFTs," in IEEE J-EDS, vol. 8, pp. 396-406, 2020

https://t.co/zk4BAp2tMj pic.twitter.com/Ay502xHy1w

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#Spanish and #French governments turn to Jitsi Meet #opensource video-conferencing platform https://t.co/68ZzP2iPq2 https://t.co/uXUBtMOAli

#Spanish and #French governments turn to Jitsi Meet #opensource video-conferencing platform https://t.co/68ZzP2iPq2 pic.twitter.com/uXUBtMOAli

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#paper: K. Xia, "New C∞ Functions for Drain–Source Voltage Clamping in Transistor Modeling," in IEEE TED, vol. 67, no. 4, pp. 1764-1768, April 2020. https://t.co/N9yGopiPNg https://t.co/9AKubeYY5x

#paper: K. Xia, "New C∞ Functions for Drain–Source Voltage Clamping in Transistor Modeling," in IEEE TED, vol. 67, no. 4, pp. 1764-1768, April 2020.https://t.co/N9yGopiPNg pic.twitter.com/9AKubeYY5x

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#paper: E. A. Gutiérrez-D., J. Méndez-V., J. C. Tinoco, E. T. Rios and O. V. Huerta-G., "DC and 28 GHz Reliability of a SOI FET Technology," in IEEE J-EDS, vol. 8, pp. 385-390, 2020. https://t.co/slotpnOx43 https://t.co/sfZjtH0CPq

#paper: E. A. Gutiérrez-D., J. Méndez-V., J. C. Tinoco, E. T. Rios and O. V. Huerta-G., "DC and 28 GHz Reliability of a SOI FET Technology," in IEEE J-EDS, vol. 8, pp. 385-390, 2020. https://t.co/slotpnOx43

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XXII ESCOLA SUL DE MICROELETRÔNICA: EMicro 2020 XXXV SIMPÓSIO SUL DE MICROELETRÔNICA: SIM 2020 27-30 April 2020 Virtual Event: https://t.co/DzzZLK7lIF Recordings: https://t.co/RuFy6pR6Qa #paper https://t.co/bItZC5bjWv

XXII ESCOLA SUL DE MICROELETRÔNICA: EMicro 2020
XXXV SIMPÓSIO SUL DE MICROELETRÔNICA: SIM 2020
27-30 April 2020
Virtual Event: https://t.co/DzzZLK7lIF
Recordings: https://t.co/RuFy6pR6Qa#paper pic.twitter.com/bItZC5bjWv

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#paper: H. Cortes-Ordonez et al., "Parameter extraction and compact drain current model for IGZO transistor from 210K up to 370K," 2020 IEEE Latin America Electron Devices Conference (LAEDC), San Jose, Costa Rica, 2020, pp. 1-5. https://t.co/WDalcLFJsX https://t.co/FJGSnemXhj

#paper: H. Cortes-Ordonez et al., "Parameter extraction and compact drain current model for IGZO transistor from 210K up to 370K," 2020 IEEE Latin America Electron Devices Conference (LAEDC), San Jose, Costa Rica, 2020, pp. 1-5. https://t.co/WDalcLFJsX pic.twitter.com/FJGSnemXhj

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#paper: X. Lu, M. Law, Y. Jiang, X. Zhao, P. Mak and R. P. Martins, "A 4um Diameter SPAD Using Less-Doped N-Well Guard Ring in Baseline 65nm CMOS," in IEEE TED, vol. 67, no. 5, pp. 2223-2225, May 2020. https://t.co/FFxEEIyh8J https://t.co/LGo5VTESKd

#paper: X. Lu, M. Law, Y. Jiang, X. Zhao, P. Mak and R. P. Martins, "A 4um Diameter SPAD Using Less-Doped N-Well Guard Ring in Baseline 65nm CMOS," in IEEE TED, vol. 67, no. 5, pp. 2223-2225, May 2020. https://t.co/FFxEEIyh8J pic.twitter.com/LGo5VTESKd

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#paper: Y. Hernández-Barrios, A. Cerdeira, M. Estrada and B. Iñíguez, "Analytical Current–Voltage Model for Double-Gate a-IGZO TFTs With Symmetric Structure for Above Threshold," in IEEE TED, vol. 67, no. 5, pp. 1980-1986, May 2020. https://t.co/mJQkQo60Th https://t.co/Z1xMTrw56o

#paper: Y. Hernández-Barrios, A. Cerdeira, M. Estrada and B. Iñíguez, "Analytical Current–Voltage Model for Double-Gate a-IGZO TFTs With Symmetric Structure for Above Threshold," in IEEE TED, vol. 67, no. 5, pp. 1980-1986, May 2020. https://t.co/mJQkQo60Th pic.twitter.com/Z1xMTrw56o

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#paper: L. Liu, W. Chen, X. Liu and G. Du, "Photoelectric Characteristic Evaluation of Different Structured UTBB MOSFETs," in IEEE TED, vol. 67, no. 5, pp. 1919-1923, May 2020 https://t.co/2onkfigdMS https://t.co/XWNv6uZML9

#paper: L. Liu, W. Chen, X. Liu and G. Du, "Photoelectric Characteristic Evaluation of Different Structured UTBB MOSFETs," in IEEE TED, vol. 67, no. 5, pp. 1919-1923, May 2020https://t.co/2onkfigdMS pic.twitter.com/XWNv6uZML9

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Online Classes on The Principle of Semiconductor Devices

Professor Mansun Chan, UST (HK), has developed a 13 weeks online class on the principle of semiconductor devices.  Unlike tradition lectures, the class use extensive animations to help students to visualize the actions of carriers in a device.  The classes was divided into two part, part I on semiconductor carrier statistics, PN Junction, BJT and part II on MOSFET and advanced FET.

• Principle of Semiconductor Devices Part I: Semiconductors, PN Junctions and Bipolar Junction Transistors
  An intuitive approach to operational principles of semiconductor devices.The course covers PN junction diodes, optical sensors, solar cells, LEDs, and Bipolar Junction Transistors.
  https://www.edx.org/course/principle-of-semiconductor-devices-part-i-semiconductors-pn-junctions-and-bipolar-junction-transistors-1
• Principle of Semiconductor Devices Part II: Field Effect Transistors and MOSFETsAn intuitive approach to operational principles of semiconductor devices. The course covers MOS capacitors, charge coupled devices, classical MOSFETs, transistor scaling, short channel MOSFET, and nano-CMOS transistors.
  https://www.edx.org/course/principle-of-semiconductor-devices-part-ii-field-effect-transistors-and-mosfets-2

Meet your instructor:

Mansun Chan

Chair Professor, Department of Electronic and Computer Engineering

The Hong Kong University of Science and Technology

The Hong Kong University of Science and Technology

conference FOSS paper reached 300 reads

D. Tomaszewski, G. Głuszko, M. Brinson, V. Kuznetsov and W. Grabinski, "FOSS as an efficient tool for extraction of MOSFET compact model parameters," 2016 MIXDES - 23rd International Conference Mixed Design of Integrated Circuits and Systems, Lodz, 2016, pp. 68-73.

Abstract - A GNU Octave - based application for device-level compact model evaluation and parameter extraction has been developed. The applications main features are as follows: experimental I–V data importing, generating input data for different circuit simulation programs, running the simulation program to calculate I–V characteristics of the specified models, calculating model misfit and its sensitivity to selected parameter variation, and the comparison of experimental and simulated characteristics. Measured I–V data stored by different measurement systems are accepted. Circuit simulations may be done with Ngspice, Qucs and LTSpiceIV © . Selected aspects of the application are presented and discussed.

Pokit PRO. Multimeter, Oscilloscope & Logger https://t.co/m65iiW8ckl #paper https://t.co/qAYsVIiW7m

Pokit PRO. Multimeter, Oscilloscope & Logger https://t.co/m65iiW8ckl #paper pic.twitter.com/qAYsVIiW7m

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#paper: J. Li, Z. Chen, Y. Qu and R. Zhang, "Traps Around Ge Schottky Junction Interface: Quantitative Characterization and Impact on the Electrical Properties of Ge MOS Devices," in IEEE J-EDS, vol. 8, pp. 350-357, 2020 https://t.co/zD5bzZH2cN https://t.co/g7qcnAGtjM

#paper: J. Li, Z. Chen, Y. Qu and R. Zhang, "Traps Around Ge Schottky Junction Interface: Quantitative Characterization and Impact on the Electrical Properties of Ge MOS Devices," in IEEE J-EDS, vol. 8, pp. 350-357, 2020https://t.co/zD5bzZH2cN pic.twitter.com/g7qcnAGtjM

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#paper: D. Arbet, L. Nagy, V. Stopjakova "Ultra-Low-Voltage IC Design Methods" Integrated Circuits/Microchips, 2020 | IntechOpen https://t.co/QuPlCt45YH https://t.co/XsJrid4jC7

#paper: D. Arbet, L. Nagy, V. Stopjakova "Ultra-Low-Voltage IC Design Methods" Integrated Circuits/Microchips, 2020 | IntechOpen https://t.co/QuPlCt45YH pic.twitter.com/XsJrid4jC7

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#paper: W. Cheng et al., "Fabrication and Characterization of a Novel Si Line Tunneling TFET With High Drive Current," in IEEE J-EDS Society, vol. 8, pp. 336-340, 2020 https://t.co/BQAZV3tf3C https://t.co/Eqw9tGmBDI

#paper: W. Cheng et al., "Fabrication and Characterization of a Novel Si Line Tunneling TFET With High Drive Current," in IEEE J-EDS Society, vol. 8, pp. 336-340, 2020
https://t.co/BQAZV3tf3C pic.twitter.com/Eqw9tGmBDI

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Fwd: "It is forbidden to spit on cats during plague-time"

-------- Forwarded message FYI ---------
From: John Cooley <jcooley@zeroskew.com>
Date: Wed, Apr 15, 2020 at 5:10 PM
Subject: users on Empyrean XTop ECOs, and Cadence Tempus vs. PrimeTime

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 STMicroelectronics: RDC signoff on CPU subsystem & Real Intent RDC
            http://www.deepchip.com/look/see200327-02.html
Mentor whitepaper Calibre faster through DRC deck optimization
            http://www.deepchip.com/look/see190517-01.html

#paper: Lin, P., Li, C., Wang, Z. et al. Three-dimensional memristor circuits as complex neural networks. Nat Electron (2020) https://t.co/9ikrvgQq3z https://t.co/MH0mVWdyVj

#paper: Lin, P., Li, C., Wang, Z. et al. Three-dimensional memristor circuits as complex neural networks. Nat Electron (2020)https://t.co/9ikrvgQq3z pic.twitter.com/MH0mVWdyVj

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#paper: Darsen D. Lu, Sourav De, Mohammed Aftab Baig, Bo-Han Qiu and Yao-Jen Lee; A computationally efficient compact model for ferroelectric FETs for the simulation of online training of neural networks; arXiv preprint arXiv:2004.03903, 2020 https://t.co/JBZfgb2jZw https://t.co/AH9NvasJuD

#paper: Darsen D. Lu, Sourav De, Mohammed Aftab Baig, Bo-Han Qiu and Yao-Jen Lee; A computationally efficient compact model for ferroelectric FETs for the simulation of online training of neural networks; arXiv preprint arXiv:2004.03903, 2020https://t.co/JBZfgb2jZw pic.twitter.com/AH9NvasJuD

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April 15, 2020 at 10:27AM
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#paper: Meng Zhang and Dragan Damjanovic; Quasi-rayleigh model for modeling hysteresis of piezoelectric actuators; Smart Materials and Structures; DOI: https://t.co/0lOX07NnAU https://t.co/WaSgY5lYML https://t.co/Dux8Lpe4wq

#paper: Meng Zhang and Dragan Damjanovic; Quasi-rayleigh model for modeling hysteresis of piezoelectric actuators; Smart Materials and Structures; DOI: https://t.co/0lOX07NnAU
https://t.co/WaSgY5lYML pic.twitter.com/Dux8Lpe4wq

— Wladek Grabinski (@wladek60) April 14, 2020

from Twitter https://twitter.com/wladek60

April 14, 2020 at 02:24PM
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ICMTS2020 #paper: Cutoff Frequency Fluctuation in RF-MOSFETs

2020 ICMTS, April 6-9, Edinburgh (UK)
Novel Statistical Modeling and Parameter Extraction Methodology
of Cutoff Frequency for RF-MOSFETs

Chika Tanaka, Yasuhiko Iguchi, Atsushi Sueoka, and Sadayuki Yoshitomi

Memory Division, Kioxia Corporation

2-5-1, Kasama, Sakae-ku, Yokohama, 247-8585, Japan

Abstract: The cutoff frequency fluctuation in RF-MOSFET has been investigated. Detailed analysis for capacitance fluctuation as well as the extraction of an intrinsic MOSFET parameter were performed. The extracted process parameters were verified by the framework of effective mobility. The global statistical model of cutoff frequency was successfully developed in terms of capacitance fluctuation, considering intrinsic (channel and bulk charge) and extrinsic (overlap and fringe) capacitance components separately and identifying the major variability sources for cutoff frequency by using extracted parameter.

Fig: Calculated σf_T is plotted against σf_T obtained from measured data.

Fwd: MIXDES 2020 moves online

------- Forwarded message ---------

From: MIXDES 2020 Organising Committee <mixdes2020@dmcs.p.lodz.pl>
Date: Thu, 9 Apr 2020 at 22:03
Subject: MIXDES 2020 moves online
To: <wladek@grabinski.ch>

Dear Colleagues,

As the Covid-19 disease is spreading worldwide and we have not yet seen
the peak, we have decided to move current edition of MIXDES to the
Internet. Hopefully next year we will be able to meet face to face. In
the meantime please keep your calendars blocked for the original
conference dates (June 25-27), and prepare to join us online. We will
inform you about the details later.

We are planning to reduce the conference fee to the level of ca. 100 Euro.

As in the previous years, the Conference Proceedings containing all the
presented papers will still be published on IEEE Xplore, so you do not
have to worry about visibility of your papers.


Wishing you Happy Easter and hoping that you stay safe,

Mariusz Orlikowski

--

Sent from Wladek's iPhone

Fwd: Immediate changes for ESSCIRC-ESSDERC 2020 in Grenoble

------- Forwarded message ---------

From: Andreia CATHELIN <andreia.cathelin@st.com>
Date: Thu, 9 Apr 2020 at 17:11
Subject: Immediate changes for ESSCIRC-ESSDERC 2020 in Grenoble
To: Andreia CATHELIN <andreia.cathelin@st.com>
CC: Andreia CATHELIN <andreia.cathelin@st.com>, Sylvain CLERC <sylvain.clerc@st.com>, Maud VINET <maud.vinet@cea.fr>, ANDRIEU François 200489 <francois.andrieu@cea.fr>, Dominique THOMAS <dominique.thomas@st.com>, ERNST Thomas 175262 <thomas.ernst@cea.fr>, andrea.baschirotto@unimib.it <andrea.baschirotto@unimib.it>, huang@iis.ee.ethz.ch <huang@iis.ee.ethz.ch>

Grenoble, April 9th, 2020

 

Dear TPC members of ESSCIRC-ESSDERC conference,

 

First of all, we truly hope this email finds you in good health, together with family and friends!

 

Together with our sponsoring IEEE Societies, SSCS and EDS, ESSCIRC-ESSDERC is closely monitoring developments related to the rapidly evolving COVID-19 pandemic. The health and safety of our members is the number one priority of our societies. As of today April the 9th, 2020, more than one third of the Global population is under severe confinement, as a result of the protective public health measures imposed by the different governments, states or provinces. The situation is still evolving rapidly and dramatically, unfortunately in an unpredictable way.

 

Given this uncertain situation, we, the organizing committee of ESSxxRC2020 Grenoble and the ESSCIRC-ESSDERC Steering committee, have decided to propose a new format for our conference:

• The presential conference with peer reviewed papers has been rescheduled to September 2021. It will take place in Grenoble led by the existing organizing team
• In addition a NEW and Virtual Education Event is being developed for September 14th 2020 consisting of 10 educational sessions (workshops and tutorial) comprising invited presentations by leading technologists. More details of the event will be released in the coming days.

 

From a practical point of view:

For all the authors who have been or were about to prepare papers for this version of ESSCIRC-ESSDERC, we strongly encourage you to submit your publications directly to the following IEEE journals:

• For ESSCIRC, please see https://sscs.ieee.org/publications:
• IEEE SSC-L, Solid-State Circuits Letters (same 4-pages format as ESSCIRC)
• The SSCS has just created a Special Section on ESSCIRC 2020, inside the SSC-Letters: https://mc.manuscriptcentral.com/ssc-l
• When submitting their manuscript, authors need to select: Special Section on ESSCIRC 2020. It is open for submissions from April 9, 2020 to May 4, 2020.
• The authors having accepted papers through this path will be kindly invited in September 2021 to present this same work in a Special Oral Session of ESSCIRC2021.
• IEEE JSSC, Journal of Solid-State Circuits
• IEEE O-JSSC, Open-Journal of Solid-State Circuits (open access)

• For ESSDERC, please see https://eds.ieee.org/publications :
• IEEE EDL, Electron Devices Letters (same 4-pages format as ESSDERC) 
• IEEE TED, Transactions on Electron Devices
• IEEE JEDS, Journal of Electron Devices Society (open access)
• We are actively working with EDS to propose a similar Special Section for ESSDERC together with ED-L.

 

In 2021, we are planning to resume to a usual conference development schedule with tentative dates of: 

• paper submission deadline on April 19th, 2021,
• the conference in Grenoble, September 6-9, 2021.

All the topology of the conference with regards to the different tracks and TPC members stays exactly the same for 2021. You might as well be solicited by the different IEEE journals for anonymous reviews, please do provide all your support, as they will get a much larger volume of publications than regular.

 

The 2022 version of ESSCIRC-ESSDERC will take place in September 2022 in Milano. We thank very much to Andrea Baschirotto&team for their immediate proactivity, flexibility and cooperation.

 

This information shall be posted as well on our website within the hour, and we will massively announce it also on social media. Please do not hesitate to spread this information to your personal network.

 

Thank you very much for your continued trust, and stay safe!

 

Kind regards,

 

Andreia Cathelin, TPC chair ESSCIRC

Francois Andrieu, TPC chair ESSDERC

Sylvain Clerc, TPC co-chair ESSCIRC

Maud Vinet, TPC co-chair ESSDERC

Thomas Ernst, Conference Chair

Dominique Thomas, Conference Co-Chair

Qiuting Huang, ESSCIRC-ESSDERC Steering Committee Chair

 

 

Andreia Cathelin | Tel: +33 476926603 | Mobile: +33 607649918

Technology & Design Platform | Strategy & Innovation/Ecosystem | Technology R&D Fellow

 

STMicroelectronics Crolles2

850 rue Jean Monnet | 38926 Crolles Cedex | France

 

Knowledge is proud that he has learned so much,
Wisdom is humble that he knows no more.

The Task, Book 6, 'The Winter Walk at Noon' (published 1785). William Cowper

 

 

 

--

Sent from Wladek's iPhone

#Resignation of Mauro Ferrari – Statement by the #ERC's Scientific Council https://t.co/7rVa8pkFnO #paper https://t.co/NoQidE1Tko

#Resignation of Mauro Ferrari – Statement by the #ERC's Scientific Council https://t.co/7rVa8pkFnO#paper pic.twitter.com/NoQidE1Tko

— Wladek Grabinski (@wladek60) April 9, 2020

from Twitter https://twitter.com/wladek60

April 09, 2020 at 09:53AM
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