Top #opensource #conference picks for #2017 https://t.co/nJzg2bSbpq #papers

Top #opensource #conference picks for #2017 https://t.co/nJzg2bSbpq #papers

— Wladek Grabinski (@wladek60) December 14, 2016

from Twitter https://twitter.com/wladek60

December 14, 2016 at 10:37AM
via IFTTT

[paper] A surface potential large signal model for AlGaN/GaN HEMTs

A surface potential large signal model for AlGaN/GaN HEMTs

Q. Wu, Y. Xu, Z. Wen, Y. Wang and R. Xu

2016 11th EuMIC, London, UK, 2016, pp. 349-352

doi: 10.1109/EuMIC.2016.7777562

Abstract: This paper presents an accurate analytical surface-potential-based compact model for AlGaN/GaN HEMTs for SPICE-like circuit simulation. Considering the important energy level E₀, an easy-implemented analytical continuous expression for the fermi level position E_f was deduced to obtain the surface potential (SP) φ_s. Then analytical core models for intrinsic charge and drain current are derived based on φ_s. The model has been implemented in Agilent ADS by using symbolic defined device. Excellent agreement of DC I-V, fundamental output power, power added efficiency and gain is obtained for the first time compared with measurement results. Moreover, the effect of physical parameter such as the barrier thickness d on device characteristic is researched on the basic of this model. The results show that the proposed physical based model can be useful for technological parameters analysis and optimization of process.

[read more: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7777562&isnumber=7777458]

Writing a science/tech book, is it that hard?

Writing a science/tech book, is it that hard?

As a microwave engineer Errikos Lourandakis, PhD, a senior R&D engineer at Helic Inc., started with RF device characterization while working on his PhD. He got fascinated about it and gradually devoted much of his time in the lab (see his lab pic below), though RF and Microwave Measurements were just a vehicle for microwave circuit design that was his actual PhD topic. After 10+ years in academia and industry, recently he has also published his new book "On-Wafer Microwave Measurements and De-embedding"

Errikos' RF and mm-Wave Measurement Lab

Is it worth it? [read more...]

[Fellowship] Physics Based Modeling Simulation and Electrical Characterization

Physics Based Modeling Simulation and Electrical Characterization 

of Quantum Effects in Multigate MOSFETs

[DRDO Fellowship]

Dr. Vimala Palanichamy is looking for Junior Research Fellowship (INR 25000 Stipend per Month) for this project funded by Defense Research and Development Organization (DRDO), Government of India. Please refer below advertisement for applying for Junior Research Fellowship for working on the project: 

http://dayanandasagar.edu/dsce/images/pdf/Advertisement_for_JRF.pdf

The #efabless $15,000 #Design #Challenge https://t.co/OV5sjnfSxm #papers

The #efabless $15,000 #Design #Challenge https://t.co/OV5sjnfSxm #papers

— Wladek Grabinski (@wladek60) November 30, 2016

from Twitter https://twitter.com/wladek60

November 30, 2016 at 01:17PM
via IFTTT

Investigation of Gate Direct-Current and Fluctuations in Organic p-Type Thin-Film Transistors #papers https://t.co/IS3MAiWqZY

Investigation of Gate Direct-Current and Fluctuations in Organic p-Type Thin-Film Transistors #papers https://t.co/IS3MAiWqZY

— Wladek Grabinski (@wladek60) November 29, 2016

from Twitter https://twitter.com/wladek60

November 29, 2016 at 02:51PM
via IFTTT

#Opensource #lab-on-a-board costs $29 https://t.co/cJIQPpDgvG #software #feedly #papers

#Opensource #lab-on-a-board costs $29 https://t.co/cJIQPpDgvG #software #feedly #papers

— Wladek Grabinski (@wladek60) November 26, 2016

from Twitter https://twitter.com/wladek60

November 26, 2016 at 08:25PM
via IFTTT

[paper] RESURF Model and Electrical Characteristics of Finger-Type STI Drain Extended MOS Transistors

RESURF Model and Electrical Characteristics of Finger-Type STI Drain Extended MOS Transistors
H. C. Tsai, R. H. Liou and C. Lien
IEEE Transactions on Electron Devices
vol. 63, no. 12, pp. 4603-4609, Dec. 2016

Abstract: Finger-type shallow trench isolation (finger STI) drain extended MOS transistors are fabricated and its electrical characteristics is studied. Polyplate on a finger STI served as a reduced surface field is adopted to enhance breakdown voltage (BV) by reducing the effective doping concentration of the drain extension (DE) finger. The conformal mapping method, which relates the reduction of the doping concentration to the width (z_o) of the DE finger, the gap (z_d) between the polyplate and the DE finger, and the STI depth (y_s), is used to estimate the reduction of the doping concentration theoretically. Based on this reduced doping concentration, a BV model is derived. The predictions of this model agree very well with the experimental data.

Keywords: Conformal mapping, Doping, Electric breakdown, MOS devices, Semiconductor process modeling, Silicon, Transistors, Drain extended MOS (DEMOS), Lateral double Diffused MOS (LDMOS), poly field plate, reduced surface field (RESURF)

doi: 10.1109/TED.2016.2605504
[read more...]

[paper] Small-Signal Characterization and Modeling of 55 nm SiGe BiCMOS HBT up to 325 GHz

Small-Signal Characterization and Modeling of 55 nm SiGe BiCMOS HBT up to 325GHz

Marina Deng^a, Thomas Quémerais^b, Simon Bouvot^a, ^b, Daniel Gloria^b, Pascal Chevalier^b

Sylvie Lépilliet^a, François Danneville^a, Gilles Dambrine^a

^aIEMN UMR CNRS 8520, University of Lille, Avenue Poincaré, CS60069, 

59652 Villeneuve-d’Ascq Cedex, France

^bSTMicroelectronics, 850 rue Jean Monnet, 38926 Crolles, France

Highlights

• The SiGe HBT full S-parameters from 250MHz to 325GHz under multiple bias conditions are presented for the first time.
• Standard calibration and de-embedding techniques are used and remained valid up to 325GHz thanks to a reduction of the test structures dimensions.
• A simple and accurate small-signal electrical model was extracted and compared with measurements up to 325GHz.

Received 19 September 2016, Revised 18 November 2016, Accepted 21 November 2016, Available online 22 November 2016 [read more...]

http://dx.doi.org/10.1016/j.sse.2016.11.012

2016 IEDM Tutorials

2016 International Electron Devices Meeting Tutorials

The tutorials are in their sixth year and are 90 minute stand-alone presentations on specialized topics taught by world-class experts. These tutorials provide a brief introduction to their respective fields, and facilitate understanding of the technical sessions. The tutorial sessions will take place on Saturday, Dec.3, 2016. Three tutorials are given in parallel in two time slots, at 2:45 p.m.and 4:30 p.m. respectively.

Topics presented at 2:45pm - 4:15pm:

• The Struggle to Keep Scaling BEOL, and What We Can Do Next
  Rod Augur, Distinguished Member of the Technical Staff, GlobalFoundries
• Physical Characterization of Advanced Devices
  Robert Wallace, Univ. Texas at Dallas
• Spinelectronics: From Basic Phenomena to Magnetoresistive Memory (MRAM) Applications
  Bernard Dieny, Chief Scientist, Spintec CEA

Topics presented at 4:30pm - 6:00pm:

• Electronic Circuits and Architectures for Neuromorphic Computing Platforms
  Giacomo Indiveri, Univ. of Zurich and ETH Zurich
• Present and Future of FEOL Reliability—from Dielectric Trap Properties to Reliable Circuit Operation
  Ben Kaczer, Principal Scientist, IMEC
• Embedded Systems and Innovative Technologies for IoT Applications
  Ali Keshavarzi, Vice President of R&D, Cypress Semiconductor

Register for the IEDM tutorials here: http://ieee-iedm.org/onsite-registration-center/online-registration/

EKV302.00 in Cadence MMSIM 14.10

EKV302.00 is available in Cadence MMSIM 14.10. The new version can be accessed through version control parameter. It includes several enhancements, new flicker noise model and new operating point features.

INFOS 2017 in Potsdam, Germany

20th Conference on “Insulating Films on Semiconductors” 

INFOS 2017

June 27th – 30th, 2017 in Potsdam, Germany

The INFOS conference is a prestigious biennial event which brings together electrical engineers, technologists, materials scientists, device physics and chemists from Europe and around the world to debate the latest development in thin insulating film technology and identify as well as address challenges ahead in this highly diversifying field [read more...]

Conference Topics:

• High-k dielectrics, metal gate materials and SiO2 for future scaling
• Gate stack materials for high mobility substrates (Ge, SiGe, GaN, III-V)
• Stacked dielectrics for non-volatile memory (flash, nc-Si)
• Dielectrics for resistive switching memories and spin memories
• Dielectrics for DRAM and MIM
• Low-k dielectrics
• Semiconductors on insulators
• Dielectrics for 2D materials, nanowires, 2D devices and carbon-based devices
• Surface cleaning technologies
• Physics and chemistry of dielectrics and defects
• Characterization techniques for dielectrics and interfaces
• Electrical reliability, leakage and modelling
• Modelling of atomic structure of dielectrics, interfaces and thin films
• Topological insulators
• Ferroelectrics and functional oxides
• Dielectrics and thin films for TFT, amorphous or organic devices and photovoltaics
• Dielectrics for photonics and sensing

Creating A PCB In Everything: KiCad, Part 1 https://t.co/gSqz7GGbnE #todo #feedly #papers

Creating A PCB In Everything: KiCad, Part 1 https://t.co/gSqz7GGbnE #todo #feedly #papers

— Wladek Grabinski (@wladek60) November 17, 2016

from Twitter https://twitter.com/wladek60

November 17, 2016 at 11:23PM
via IFTTT

Open Source License Compliance bei Embedded-Systemen

Open Source License Compliance bei Embedded-Systemen 

( Kompaktseminar, ESE Kongress 2016, in Sindelfingen )

Referent: Dr. Till Jaeger, JBB Rechtsanwälte

Zeit: 28.11.16 09:00-12:30

Abstract: When using Linux and other open source software (OSS), the license terms of the GPL and other open source licenses must be adhered to. As license violations lead directly to copyright infringements, appropriate compliance measures are necessary. The compact seminar presents the essential requirements for a compliance process based on the OpenChain Initiative. OpenChain aims at an international standard for suppliers using OSS in your products.

Outline:

1. What is Open Source Software?
2. How does the open source license model work?
3. Legal consequences of violation of OSS license terms
4. How is it ensured that the use of OSS is known and which licensing conditions are affected?
5. The Copyleft (1): When must self-development be released again as OSS?
6. Copyleft (2): Verification of license compatibility between different OSS licenses
7. Process to comply with sales obligations (for example, source code offer, co-delivery license texts)
8. Methods of quality control

[read more...]

National Workshop on Advanced Nanoscale Device Design Using TCAD

The National Workshop on Advanced Nanoscale Device Design Using Technology Computer-Aided Design (TCAD) was organized by the IEEE SolidState Circuits Society (SSCS) College of Engineering Chengannur, India Chapter. The workshop was held 28 December 2015 through 1 January 2016 as a three-day tutorial and two-day handson session. The event was graced with the presence of distinguished lecturers from top institutions in India, including Prof. Yogesh S. Chouhan from IIT Kanpur delivering the keynote talk. The workshop attracted approximately 150 participants from 15 reputable academic institutions. People from industry and also attended the event.

The coordinators were proud to present a successful workshop as one of the first events since the formation of the Chapter. The event was funded by the SSCS extra subsidy program. The feedback received from the attendees was very positive. Each participant received a certificate during the closing ceremony of the event. The five-day workshop came to an end by the heartfelt vote of thanks by Nisha Kuruvilla, with a motto “This is just the beginning.” [read more...]

[paper] Analysis of aging effects - From transistor to system level

Analysis of aging effects - From transistor to system level

Maike Taddiken*, Nico Hellwege, Nils Heidmann, Dagmar Peters-Drolshagen, Steffen Paul

Institute of Electrodynamics and Microelectronics,
University of Bremen, Otto-Hahn-Allee 1, Bremen 28359,Germany

ABSTRACT: Due to shrinking feature sizes in integrated circuits, additional reliability effects have to be considered which influence the functionality of the system. These effects can either result from the manufacturing process or external influences during the lifetime such as radiation and temperature. Additionally, modern technology nodes are affected by time-dependent degradation i.e. aging. Due to the age-dependent degradation of a circuit, processes on the atomic scale of the semiconductor material lead to charges in the oxide silicon interface of CMOS devices, altering the performance parameters of the device and subsequently the behavior of the circuit. With the continuous downscaling of modern semiconductor technologies, the impact of these atomic scale processes affecting the overall system characteristics becomes more and more critical. Therefore, aging effects need to be assessed during the design phase and actions have to be taken guaranteeing the correct system functionality throughout a system’s lifetime. This work presents methods to investigate the influence of age-dependent degradation as well as process variability on different levels. An operating-point dependent sizing methodology based on the gm/ID method extended to incorporate aging, which aims at developing aging-resistent circuits is presented. The basic idea of the gm/ID sizing method is the dependence of the operating point of a MOS transistor on the state of inversion in the channel, its strong relation to circuit performance and the possibility to calculate transistor dimensions.The inversion coefficient IC is a fundamental metric within the gm/ID method and numerically represents the inversion level of a MOS device formally described in the EKV MOS model. Additionally, the sensitivity of circuit performances in regard to aging can be determined. In order to investigate the reliability of a complex system on behavioral level, a modeling method to represent the performance of system components in dependence of aging and process variability is introduced. [read more...]

ICNF 2017: 2nd Call for Papers

24th International Conference on Noise and Fluctuations (ICNF 2017) 

20-23 of June 2017 in Vilnius, Lithuania

We would like to invite you to submit your abstracts. For submission of the abstracts, please, REGISTER and go to the Abstract submission site. Instruction for authors and templates for abstract preparation can be found and downloaded  at the Conference website: http://www.icnf2017.ff.vu.lt/paper-submission/instructions-for-authors
Deadline of the abstract submission is 22 January, 2017

Please also keep in mind ICNF2017 important dates:

• Abstract submission deadline: 22 January, 2017
• Notification of acceptance deadline: 27 February, 2017
• Full paper submission deadline:27 March, 2017
• Early bird registration: 19 April, 2017
• Conference: 20-23 June, 2017

Please share this information to your colleagues and those who might be interested in ICNF 2017.

For more information visit the Conference website: http://www.icnf2017.ff.vu.lt/
or contact us: icnf2017@ff.vu.lt

Looking forward to meeting you in Vilnius.

With best regards,
Sandra Pralgauskaitė and Paulius Sakalas - Organizing Committee Chairs

[mos-ak] [Final Program] 9th International MOS-AK Workshop Berkeley DEC.7, 2016

9th International MOS-AK Workshop  

  Berkeley December 7, 2016 
    Final Workshop Program 

 
Together with the MOS-AK workshop host, Prof. Jaijeet Roychowdhury, UCB and International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to the 9th International MOS-AK Workshop which will be held at EECS Department, University of California, Berkeley on December, 7, 2016. Planned MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Important Dates:

• Preannouncement - Sept. 2016
  
• Call for Papers - Oct. 2016
  
• Final Workshop Program - Nov. 2016
  
• MOS-AK Workshop - Dec. 7 2016
•   9:00-12:00 Morning Session
• 13:00-16:00 Afternoon Session

Venue:

540 Cory Hall 
EECS Department
University of California, Berkeley
Directions to the DOP Center in Cory Hall
See also http://www.eecs.berkeley.edu/Directions/

Final MOS-AK/Berkeley Workshop Program Online 

http://www.mos-ak.org/berkeley_2016/

Online Workshop Registration:

http://www.mos-ak.org/berkeley_2016/registration.php
(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

WG10112016

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