Nov 16, 2017
Innovations in Electronics and Communication Engineering
Nov 14, 2017
The Pentagon is set to make a big push toward #opensource software next year https://t.co/EMWCKvEoQM
The Pentagon is set to make a big push toward #opensource software next year https://t.co/EMWCKvEoQM
— Wladek Grabinski (@wladek60) November 14, 2017
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November 14, 2017 at 10:45PM
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3 #opensource alternatives to AutoCAD https://t.co/ysUQCGiq8X https://t.co/V68oi64jF3
3 #opensource alternatives to AutoCAD https://t.co/ysUQCGiq8X http://pic.twitter.com/V68oi64jF3
— Wladek Grabinski (@wladek60) November 14, 2017
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November 14, 2017 at 10:38AM
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7th All-Russian Workshop on CAD of IC Design
08:45 - 09:15 | Registration (University entrance) |
09:30 - 13:00 | Conference hall 3rd floor of the main lecture building |
- Synthesis in Genus (28nm technology) | |
- Introduction to Joules | |
- Innovus 17.1 Topical Introduction | |
13:00 - 14:00 | Lunch break |
14:00 - 18:15 | Conference hall 3rd floor of the main lecture building |
- Introduction to Stylus | |
- Physical verification with the help of PVS | |
- A new generation of verification software - Xcelium and Indago | |
- The history and future of megatrends in EDA |
9:00 - 18:00 | Laboratory V-315 of the Department of Electronics (Practical classes) |
- Behavioral modeling | |
- Logical synthesis | |
- Simulation of a Verilog modules with element delays | |
- Physical design of the digital modules | |
- Verification of the digital modules |
10:00 - 12:00 | Laboratory V-315 of the Department of Electronics |
- Working discussions, summarizing |
Contact Event Secretary: E. Atkin
+7 495 7885699 ext. 9155
+7 499 3242597
Nov 11, 2017
#paper A temperature‐dependent surface potential‐based algorithm for extraction of Vth in homojunction TFETs https://t.co/uhg1laMLY2
#paper A temperature‐dependent surface potential‐based algorithm for extraction of Vth in homojunction TFETs https://t.co/uhg1laMLY2
— Wladek Grabinski (@wladek60) November 11, 2017
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November 11, 2017 at 07:15PM
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#Tesla-inspired Chinese EV startup launches all-electric SUV using #opensource patents https://t.co/LYByI2RCyr
#Tesla-inspired Chinese EV startup launches all-electric SUV using #opensource patents https://t.co/LYByI2RCyr
— Wladek Grabinski (@wladek60) November 11, 2017
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November 11, 2017 at 09:39AM
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Nov 7, 2017
ngspice release 27, September 17th, 2017 https://t.co/0jSKnj19no #Modeling https://t.co/c5INhqX0yD
ngspice release 27, September 17th, 2017 https://t.co/0jSKnj19no #Modeling http://pic.twitter.com/c5INhqX0yD
— Wladek Grabinski (@wladek60) November 7, 2017
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November 07, 2017 at 08:36PM
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Nov 6, 2017
A Near-Threshold Voltage Oriented Library for High-Energy Efficiency and Optimized Performance in 65nm CMOS https://t.co/OOQYhqgx9U #paper
A Near-Threshold Voltage Oriented Library for High-Energy Efficiency and Optimized Performance in 65nm CMOS https://t.co/OOQYhqgx9U #paper
— Wladek Grabinski (@wladek60) November 6, 2017
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November 06, 2017 at 08:26PM
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Nov 3, 2017
[paper] Validation of MOSFET Model Source–Drain Symmetry
doi: 10.1109/TED.2006.881005
Nov 2, 2017
Circuit-aging #modeling based on dynamic MOSFET degradation and its verification (#SISPAD) https://t.co/QgJ5UIe7Yx
Circuit-aging #modeling based on dynamic MOSFET degradation and its verification (#SISPAD) https://t.co/QgJ5UIe7Yx
— Wladek Grabinski (@wladek60) November 2, 2017
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November 02, 2017 at 10:43AM
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Analytical #modeling is both science and art https://t.co/DBdMqRJqkU https://t.co/G45cufzKTb
Analytical #modeling is both science and art https://t.co/DBdMqRJqkU http://pic.twitter.com/G45cufzKTb
— Wladek Grabinski (@wladek60) November 2, 2017
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November 02, 2017 at 10:07AM
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#Modeling of flicker noise in quasi-ballistic FETs - IEEE Conference Publication https://t.co/JpropPaK27
#Modeling of flicker noise in quasi-ballistic FETs - IEEE Conference Publication https://t.co/JpropPaK27
— Wladek Grabinski (@wladek60) November 2, 2017
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November 02, 2017 at 10:05AM
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Circuit-aging #modeling based on dynamic MOSFET degradation and its verification - IEEE Conference Publication https://t.co/QnZG525Y7R
Circuit-aging #modeling based on dynamic MOSFET degradation and its verification - IEEE Conference Publication https://t.co/QnZG525Y7R
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November 02, 2017 at 10:04AM
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Oct 31, 2017
[mos-ak] [2nd Announcement and Call for Papers] 10th International MOS-AK Workshop in the Silicon Valley
Planned,10th MOS-AK workshop organized in the Silicon Valley, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors.
Important Dates:
- Call for Papers - Sept. 2017
- 2nd Announcement - Oct. 2017
- Final Workshop Program - Nov. 2017
- MOS-AK Workshop - Dec.6, 2017
Cadence Design Systems2655 Seely AveSan Jose, CA 95134
Topics to be covered include the following among other related to the compact/SPICE modeling :
- Compact Modeling (CM) of the electron devices
- Advances in semiconductor technologies and processing
- Verilog-A language for CM standardization
- New CM techniques and extraction software
- Open Source TCAD/EDA modeling and simulation
- CM of passive, active, sensors and actuators
- Emerging Devices, TFT, CMOS and SOI-based memory cells
- Microwave, RF device modeling, high voltage device modeling
- Nanoscale CMOS devices and circuits
- Technology R&D, DFY, DFT and reliability/ageing IC Designs
- Foundry/Fabless Interface Strategies
Online Workshop Registration
Postworkshop Publications:
in a special issue of the International Journal of High Speed Electronics and Systems
Extended MOS-AK Committee
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[paper] Review of physics-based compact models for emerging nonvolatile memories
https://doi.org/10.1007/s10825-017-1098-0
SSCS Members Who Are 2017 IEEE Fellows
Oct 30, 2017
How to pick a #winning #IoT #business #model https://t.co/YjMfxPAEZB https://t.co/SDOt080Ka6
How to pick a #winning #IoT #business #model https://t.co/YjMfxPAEZB http://pic.twitter.com/SDOt080Ka6
— Wladek Grabinski (@wladek60) October 30, 2017
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October 30, 2017 at 03:39PM
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FOSDEM 2018 CAD and Open Hardware Devroom Call for Participation
- Printed Circuit Board (PCB) design tools (e.g. KiCad and gEDA)
- Analogue and digital simulators (e.g. ngspice, Qucs, Gnucap, Xyce,GHDL, Icarus and Verilator)
- Any other EDA tools such as high-level tools for digital hardware design (e.g. Migen) and HDL synthesis tools (e.g. Yosys)
- Field solvers such as openEMS
- Mechanical 2D and 3D CAD tools such as LibreCAD, FreeCAD, OpenSCAD andSolveSpace
- Open Hardware projects such as the Teres laptop and the lowRISC SoC
- Inter-project opportunities for collaboration
- 1 December 2017: deadline for submission of proposals
- 8 December 2017: announcement of final schedule
- 3 February 2018: devroom day
Oct 26, 2017
#Modeling the Performance of Nano Machined CMOS Transistors for Uncooled IR Sensing https://t.co/p4RnuHkJiZ
#Modeling the Performance of Nano Machined CMOS Transistors for Uncooled IR Sensing https://t.co/p4RnuHkJiZ
— Wladek Grabinski (@wladek60) October 26, 2017
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October 26, 2017 at 11:26AM
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Oct 25, 2017
UNIST Researchers Develop Highly Stable #Perovskite #Solar #Cells https://t.co/g1CN5I44r1 #paper... https://t.co/WSUSekJ1ky
UNIST Researchers Develop Highly Stable #Perovskite #Solar #Cells https://t.co/g1CN5I44r1 #paper... https://t.co/WSUSekJ1ky
— Wladek Grabinski (@wladek60) October 25, 2017
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October 25, 2017 at 08:47PM
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UNIST Researchers Develop Highly Stable #Perovskite #Solar #Cells https://t.co/g1CN5I44r1 #paper https://t.co/p6Jr0nPqF1
UNIST Researchers Develop Highly Stable #Perovskite #Solar #Cells https://t.co/g1CN5I44r1 #paper http://pic.twitter.com/p6Jr0nPqF1
— Wladek Grabinski (@wladek60) October 25, 2017
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October 25, 2017 at 08:47PM
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Novel Superjunction #LDMOS (>950 V) With a Thin Layer #SOI https://t.co/1NqFJ4rAZB #paper https://t.co/LglxkaZ9PP
Novel Superjunction #LDMOS (>950 V) With a Thin Layer #SOI https://t.co/1NqFJ4rAZB #paper https://t.co/LglxkaZ9PP
— Wladek Grabinski (@wladek60) October 25, 2017
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October 25, 2017 at 11:59AM
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Novel Superjunction #LDMOS (>950 V) With a Thin Layer #SOI https://t.co/1NqFJ4rAZB #paper
Novel Superjunction #LDMOS (>950 V) With a Thin Layer #SOI https://t.co/1NqFJ4rAZB #paper
— Wladek Grabinski (@wladek60) October 25, 2017
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October 25, 2017 at 11:59AM
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A Planar Junctionless FET Using SiC With Reduced Impact of Interface Traps: Proposal and Analysis https://t.co/g3qPsLKIqB #paper
A Planar Junctionless FET Using SiC With Reduced Impact of Interface Traps: Proposal and Analysis https://t.co/g3qPsLKIqB #paper
— Wladek Grabinski (@wladek60) October 25, 2017
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October 25, 2017 at 11:34AM
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Oct 24, 2017
Cryogenic characterization of CMOS technologies
Oct 19, 2017
#opensource Summit Europe 2017 https://t.co/c1TgRIgzVE https://t.co/RZqPRisbbS
#opensource Summit Europe 2017 https://t.co/c1TgRIgzVE http://pic.twitter.com/RZqPRisbbS
— Wladek Grabinski (@wladek60) October 18, 2017
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October 18, 2017 at 11:41PM
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Oct 17, 2017
A Compact QS Terminal Charge and Drain Current #Model for DG Junctionless Transistors and Its Circuit Validation https://t.co/hTsw5blL8f
A Compact QS Terminal Charge and Drain Current #Model for DG Junctionless Transistors and Its Circuit Validation https://t.co/hTsw5blL8f
— Wladek Grabinski (@wladek60) October 17, 2017
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October 17, 2017 at 11:26AM
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[paper] Accurate diode behavioral model with reverse recovery
- The complex robust time and area scalable Verilog-A model of diode containing reverse recovery effect has been developed.
- Due to implemented reverse recovery effect the model is useful especially for high-speed or high-voltage power devices.
- The model can be used as stand-alone 2-terminal diode or as a parasitic p-n junction of more complex lumped macro-model.
- Two methods of model parameter extraction or model validation have been demonstrated.
ABSTRACT: This paper deals with the comprehensive behavioral model of p-n junction diode containing reverse recovery effect, applicable to all standard SPICE simulators supporting Verilog-A language. The model has been successfully used in several production designs, which require its full complexity, robustness and set of tuning parameters comparable with standard compact SPICE diode model. The model is like standard compact model scalable with area and temperature and can be used as a stand-alone diode or as a part of more complex device macro-model, e.g. LDMOS, JFET, bipolar transistor. The paper briefly presents the state of the art followed by the chapter describing the model development and achieved solutions. During precise model verification some of them were found non-robust or poorly converging and replaced by more robust solutions, demonstrated in the paper. The measurement results of different technologies and different devices compared with a simulation using the new behavioral model are presented as the model validation. The comparison of model validation in time and frequency domains demonstrates that the implemented reverse recovery effect with correctly extracted parameters improves the model simulation results not only in switching from ON to OFF state, which is often published, but also its impedance/admittance frequency dependency in GHz range. Finally the model parameter extraction and the comparison with SPICE compact models containing reverse recovery effect is presented [read more...]
Oct 15, 2017
Software #model multi-level #photonic #IC designs https://t.co/24rtqqVTBH
Software #model multi-level #photonic #IC designs https://t.co/24rtqqVTBH
— Wladek Grabinski (@wladek60) October 14, 2017
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October 15, 2017 at 01:05AM
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Oct 12, 2017
5 #benefits of contributing to #opensource projects https://t.co/qKsBgkR9Uh
5 #benefits of contributing to #opensource projects https://t.co/qKsBgkR9Uh
— Wladek Grabinski (@wladek60) October 12, 2017
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October 12, 2017 at 09:30AM
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Oct 9, 2017
Intern/Student in SW Eng. for Power Management f/m
Your main tasks in this full time position min 5 months up to 12 months will be to:
- Create several functions/add-ons enhancing entry interface
- Develop a compiler to better explore new chip architectures-Integrate compiler output with existing tools
- Implement sanity checkers detecting
- Develop test scenarios and requirements for chip validation
- Contribute to the reporting and documentation for other teams and management
Oct 7, 2017
#Linux Now Has its First #OpenSource #RISC-V Processor https://t.co/cdM2NNXBoE
#Linux Now Has its First #OpenSource #RISC-V Processor https://t.co/cdM2NNXBoE
— Wladek Grabinski (@wladek60) October 7, 2017
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October 07, 2017 at 11:33PM
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Oct 5, 2017
#Apple #Opensource-d the #iOS Kernel for #ARM CPUs https://t.co/LUUYUnRSm2 https://t.co/91YMe1jKV1
#Apple #Opensource-d the #iOS Kernel for #ARM CPUs https://t.co/LUUYUnRSm2 http://pic.twitter.com/91YMe1jKV1
— Wladek Grabinski (@wladek60) October 5, 2017
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October 05, 2017 at 12:06PM
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Oct 2, 2017
[paper] A Novel Reconfigurable sub-0.25V Digital Logic Family Using the Electron-Hole Bilayer TFET
Sep 26, 2017
[mos-ak] [press note] 15th MOS-AK Workshop at ESSDERC/ESSCIRC September 11, 2017 Leuven
- 10th International MOS-AK Workshop in Silicon Valley (US) Dec. 2017
- Spring MOS-AK Workshop in Strasbourg (F) March 2018
- 3rd Sino MOS-AK Workshop in Beijing (CN) June, 2018
- 16th MOS-AK ESSDERC/ESSCIRC Workshop in Dresden (D) Sept, 2018
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Sep 19, 2017
A Large-Signal Monolayer Graphene Field-Effect Transistor Compact #Model for RF-Circuit Applications https://t.co/zoPkw74IK2
A Large-Signal Monolayer Graphene Field-Effect Transistor Compact #Model for RF-Circuit Applications https://t.co/zoPkw74IK2
— Wladek Grabinski (@wladek60) September 19, 2017
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September 19, 2017 at 03:55PM
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Conduction Mechanisms in Metal-Base Vertical Organic Transistors by DC and LF-Noise Measurements https://t.co/ZSiOLFMquC #paper
Conduction Mechanisms in Metal-Base Vertical Organic Transistors by DC and LF-Noise Measurements https://t.co/ZSiOLFMquC #paper
— Wladek Grabinski (@wladek60) September 19, 2017
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September 19, 2017 at 03:07PM
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#Modeling of #Electromechanical Sensors & Systems https://t.co/K40OGzRV4U https://t.co/rdih9lNeei https://t.co/748KTEgqk7
#Modeling of #Electromechanical Sensors & Systems https://t.co/K40OGzRV4U http://pic.twitter.com/rdih9lNeei https://t.co/748KTEgqk7
— Wladek Grabinski (@wladek60) September 19, 2017
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September 19, 2017 at 12:08PM
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#Modeling of #Electromechanical Sensors & Systems https://t.co/K40OGzRV4U https://t.co/rdih9lNeei
#Modeling of #Electromechanical Sensors & Systems https://t.co/K40OGzRV4U http://pic.twitter.com/rdih9lNeei
— Wladek Grabinski (@wladek60) September 19, 2017
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Sep 18, 2017
[paper] Design techniques for low-voltage analog integrated circuits
Sep 15, 2017
[paper] Principles and Trends in Quantum Nano-Electronics and Nano-Magnetics for Beyond-CMOS Computing
Principle 1: Beyond-CMOS circuits require CMOS as an integral part. They will work alongside and augment CMOS computing blocks.
Principle 2: Some devices utilize collective states; this confers advantages of non-volatility or more energy efficient operation.
Principle 3: The choice for an optimal beyond-CMOS device will be determined by compatibility with an efficient and effective interconnect.
Principle 4: Low voltage devices – most direct way to low energy operation.
Principle 5: Start benchmarking with bottom up modeling of devices, build up from simple to more complicated circuits.
Principle 6: Majority gates (if easily implemented in a certain technology) enable more efficient circuits, especially for more complex computation functions.
Principle 7: Use electrical interconnects for longer propagation spans.
Principle 8: To convince the wider community, a non- volatile computing paradigm needs to be general enough to prove that it is valid for more than one architecture; while it needs to be specific enough to dispel claims that an essential aspect is missed.
Principle 9: Neuromorphic computing can be done more efficiently with beyond-CMOS circuits.