Circuit Design and Simulation Project using eSim

Invitation to participate in Circuit Design and Simulation Project using eSim

The FOSSEE (Free and Open Source Software for Education) project based at lIT Bombay has initiated a Circuit Design and Simulation Project using esim (an open source EDA tool for circuit design, simulation, analysis and PCB design).

Interested candidates can take any solved electronic circuit from any source and redesign it using eSim and submit it to us. Candidates will be rewarded with certificates and honorarium after a review process. These circuits will also be published on our website under an appropriate open source license. 

For more details, please visit: http://esim.fossee.in/circuit-simulation-project

Analysis of Short-Channel Effects in Junctionless DG MOSFETs #papers https://t.co/P2sqAueamw

Analysis of Short-Channel Effects in Junctionless DG MOSFETs #papers https://t.co/P2sqAueamw

— Wladek Grabinski (@wladek60) July 26, 2017

from Twitter https://twitter.com/wladek60

July 26, 2017 at 11:39AM
via IFTTT

[paper] A Compact Model for the Statistics of the Low-Frequency Noise of MOSFETs With Laterally Uniform Doping

M. Banaszeski da Silva, H. P. Tuinhout, A. Zegers-van Duijnhoven, G. I. Wirth and A. J. Scholten

"A Compact Model for the Statistics of the Low-Frequency Noise of MOSFETs With Laterally Uniform Doping" 

in IEEE TED, vol. 64, no. 8, pp. 3331-3336, Aug. 2017.
doi: 10.1109/TED.2017.2713301

Abstract: In this paper, we develop a compact physics-based statistical model for random telegraph noise-related low-frequency noise in bulk MOSFETS with laterally uniform doping. The proposed model is suited for modern compact device models, such as PSP, BSIM, and EKV. With our proposed model, one can calculate the expected value and the variability of the noise as a function of bias and device parameters. We validate the model through numerous experimental results from different CMOS nodes, down to 40 nm [read more...]

[paper] Compact On-Wafer Test Structures for Device RF Characterization

B. Kazemi Esfeh, K. Ben Ali and J. P. Raskin IEEE Fellow

Compact On-Wafer Test Structures for Device RF Characterization

in IEEE TED, vol. 64, no. 8, pp. 3101-3107, Aug. 2017
doi: 10.1109/TED.2017.2717196

Abstract: The main objective of this paper is to validate the radio frequency (RF) characterization procedure based on compact test structures compatible with 50um pitch RF probes. It is shown that by using these new test structures, the layout geometry and hence the on-chip space consumption for complete sets of passive and active devices, e.g., coplanar waveguide transmission lines and RF MOSFETs, is divided by a factor of two. The validity domain of these new compact test structures is demonstrated by comparing their measurement results with classical test structures compatible with 100–150um pitch RF probes. 50um -pitch de-embedding structures have been implemented on 0.18um RF silicon-on-insulator (SOI) technology. Cutoff frequencies and parasitic elements of the RF SOI transistors are extracted and the RF performance of trap-rich SOI substrates is analyzed under small- and large-signal conditions [read more...]

[mos-ak] [2nd Announcement and Call for Papers] 15th MOS-AK ESSDERC/ESSCIRC Workshop

MOS-AK ESSDERC/ESSCIRC Workshop
http://www.mos-ak.org/leuven_2017/
September 11, 2017 Leuven
2nd Announcement and Call for Papers

Together with the ASCENT Network represented by Profs Jim Greer and Nicolas Cordero as well as  International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) and all the Extended MOS-AK TPC Committee, we have pleasure to invite to the 15th MOS-AK Compact Modeling Workshop which will be organized for consecutive 15time as in integral part of the ESSDERC/ESSCIRC Conference in Leuven on Sept.11, 2017.

Planned MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors.

Important Dates:

• Preannouncement - March 2017
• Call for Papers - June 2017
• Final Workshop Program - August 2017
• MOS-AK Workshop - Sept.11, 2017

Venue: Leuven (B) <http://www.esscirc-essderc2017.org/venue>

Topics to be covered include the following among other related to the compact/SPICE modeling :

• Compact Modeling (CM) of the electron devices
• Advances in semiconductor technologies and processing
• Verilog-A language for CM standardization
• New CM techniques and extraction software
• Open Source TCAD/EDA modeling and simulation
• CM of passive, active, sensors and actuators
• Emerging Devices, TFT, CMOS and SOI-based memory cells
• Microwave, RF device modeling, high voltage device modeling
• Nanoscale CMOS devices and circuits
• Technology R&D, DFY, DFT and reliability/ageing IC Designs
• Foundry/Fabless Interface Strategies

Speakers: (tentative list in alphabetic order)

• Nicolas Cordero, Tyndal (IRL)
• Denis Flandre, CUL (B)
• Jim Greer, Tyndal (IRL)
• Benjamin Iniguez URV (SP)
• Marcelo Pavanello, FEI (BR)
• Jean-Pierre Raskin, CUL (B)
• Wim Schoenmaker, Magwel (B)
• Chika Tanaka, Toshiba (J)
• Ashkhen Yesayan, IRPhE (AM)

Prospective authors should submit abstract online

Manuscript submission deadline: 31sth July 2017 (Monday)
(any related inquiries can be sent to papers@mos-ak.org)

Online Workshop Registration

using online registration form <http://www.esscirc-essderc2017.org/howtoregister>
(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:

Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

WG080717

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[paper] A Compact Model for the Statistics of the Low-Frequency Noise of MOSFETs With Laterally Uniform Doping

A Compact Model for the Statistics of the Low-Frequency Noise of MOSFETs With Laterally Uniform Doping

M. Banaszeski da Silva; H. P. Tuinhout; A. Zegers-van Duijnhoven; G. I. Wirth; A. J. Scholten;

in IEEE Transactions on Electron Devices, vol.PP, no.99, pp.1-6
doi: 10.1109/TED.2017.2713301

Abstract: In this paper, we develop a compact physics-based statistical model for random telegraph noise-related low-frequency noise in bulk MOSFETS with laterally uniform doping. The proposed model is suited for modern compact device models, such as PSP, BSIM, and EKV. With our proposed model, one can calculate the expected value and the variability of the noise as a function of bias and device parameters. We validate the model through numerous experimental results from different CMOS nodes, down to 40 nm. [read more...]

Multiple Honors for E3S Theme Leader, Professor Tsu-Jae King Liu

(March 1, 2017) –   The Center for Energy Efficient Electronics Science is proud to announce Prof. Tsu-Jae King Liu has been named a newly elected member of the National Academy of Engineering. Prof. King Liu, who leads the E³S Nanomechanics theme was elected this year as one of only three members from UC Berkeley to this highest professional honor to an engineer. Last year in August, Prof. King Liu has also been chosen to serve on the Board of Directors at Intel Corporation. She was welcomed by Intel Chairman Andy Bryant: “[Prof. King Liu] brings a wealth of expertise in silicon technology and innovation that will be valuable for Intel in many areas as we navigate a significant business transition while continuing to lead in advancing Moore’s Law and harnessing its economic value.”In addition to this distinguished honor by Intel, last year the Semiconductor Research Corporation (SRC) announced Prof. King Liu has been selected to receive the 2016 SRC Aristotle Award. This esteemed award was created by the SRC Board of Directors in March 1995 with the intent "to acknowledge outstanding teaching in its broadest sense, emphasizing student advising and teaching." Heartiest congratulations from the entire E³S community to Prof. King Liu for these prestigious honors!

[paper] Design Strategies for Ultralow Power 10nm FinFETs

Design Strategies for Ultralow Power 10nm FinFETs

Abhijeet Walkea^a, Garrett Schlenvogtb^b, Santosh Kurineca^a

^aDepartment of Electrical & Microelectronic Engineering, RIT, New York, USA

^bTCAD Application Engineer, Silvaco

Received 12 June 2017, Accepted 19 June 2017, Available online 20 June 2017

Abstract: In this work, new design strategies for 10nm node NMOS bulk FinFET transistors are investigated to meet low power (LP) (20pA/μm< I_OFF <50pA/μm) and ultralow power (ULP) (I_OFF <20pA/μm) requirements using three dimensional (3D) TCAD simulations. The punch-through stop implant, source and drain junction placement and gate workfunction are varied in order to study the impact on the OFF-state current (I_OFF), transconductance (g_m), gate capacitance (C_gg) and intrinsic frequency (f_T). It is shown that the gate length of 20nm for the 10nm node FinFET can meet the requirements of LP transistors and ULP transistors by source-drain extension engineering, punch-through stop doping concentration, and choice of gate workfunction.

[read more https://doi.org/10.1016/j.sse.2017.06.012]

Rising SOI tide lifts Soitec into profit

Soitec SA (Bernin, France), developer of the "smart cut" method of silicon-on-insulator (SOI) wafer production, has reported its first profit for many years and is preparing to invest in facilities in France and possibly Singapore to meet rising demand for SOI wafers...

https://shar.es/1BtAZy


Sent using ShareThis

[C4P] IEDM 2017

2017 IEDM CALL FOR PAPERS

The Annual International Electron Devices Meeting will be held at the Hilton San Francisco Union Square San Francisco, CA December 2-6, 2017

Abstract Deadline (four page final paper): August 2nd, 2017

To provide faster dissemination of the conference’s cutting-edge results, the abstract submission deadline has been moved to August 2nd for submission of four-page, camera-ready abstracts. Accepted papers will be published as-is in the proceedings

A Call for Papers flyer is available here: IEDM 2017 Call For Papers.

Customized Call for Papers for each of the technical subcommittee areas are also available:

• Circuit and Device Interaction (CDI)
• Characterization, Reliability, and Yield (CRY)
• Compound Semiconductor and High Speed Devices (CHS)
• Memory Technology (MT)
• Modeling and Simulation (MS)
• Material and interface modeling 
• Compact models
• Kinetic Monte Carlo and Molecular Dynamics
• Reliability and variability modeling
• Technology benchmarking
  New or trending areas include:
• First principle based quantum transport
• Process simulation with atomistic methods
• Self heating, interconnect and packaging
• Nano Device Technology (NDT)
• Optoelectronics, Displays, and Imagers (ODI)
• Power Devices (PD)
• Process and Manufacturing Technology (PMT)
• Sensors, MEMS, and BioMEMS (SMB)

[paper] Well-Posed Device Models for Electrical Circuit Simulation

Well-Posed Device Models for Electrical CircuitSimulation
A Guide to Creating Robust Device Models
A. Gokcen Mahmutoglu, Tianshi Wang, Archit Gupta and Jaijeet Roychowdhury
March 25, 2017

Synopsis: This document provides guidelines for creating computational device models that work well in simulation. We build our discussion around the mathematical notion of “well-posedness”. We show that the requirements for a model to be well-posed stem from the internal working mechanisms of simulators. Therefore, our main aim is to provide insight into the numerical procedures used by simulators in order to help model developers avoid ill-posedness issues. We start our discussion with an example that shows how an ill-posed Verilog-A model can produce different simulation results in different simulators. We then provide a step-by-step simulation case study. In this case study, we illustrate the role of device models in simulations by examining the steps a simulator goes through, from taking a netlist as input to producing a simulation result as output. Finally, we distill our discussion in a functional definition of a well-posed model. As an extension to our theoretical discussion, we also provide practical guidelines that should be followed by Verilog-A models in order to avoid ill-posedness issues [read more...]

This document is published as a part of the Nano-Engineered Electronic Device Simulation (NEEDS) initiative. NEEDS is an NSF-funded initiative whose charter includes the development of tools and techniques for the production of high-quality device models¹:
NEEDS has a vision for a new era of electronics that couples the power of billion-transistor CMOS technology with the new capabilities of emerging nano-devices and a charter to create high-quality models and a complete development environment that enables a community of compact model developers.

NEEDS Team: Purdue, MIT, UC Berkeley, and Stanford.”

¹For more information about NEEDS please visit https://nanohub.org/groups/needs/.

[mos-ak] [Workshop Program] 2nd Sino MOS-AK Workshop in Hangzhou June 29-30, 2017

2nd Sino MOS-AK Workshop
Hangzhou June 29-30, 2017
Workshop Program online http://www.mos-ak.org/hangzhou_2017/

 
Together with the Honorary Committee Chair LingLing Sun, HangZhou Dianzi University and International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) as well as the local coordinator Min Zhang, XMOD (Shanghai) and all the Extended MOS-AK TPC Members, we have pleasure to invite to the 2nd Sino MOS-AK Workshop in Hangzhou on June 29-30, 2017. The MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to the compact/SPICE modeling and its Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Important Dates:

• 2nd Announcement - April 2017
• Final Workshop Program - June 2017
• 2nd Sino MOS-AK Workshop - June 29-30, 2017
• 1st Day MOS-AK Workshop
• 2nd Day MOS-AK Workshop

Venue:

会议场所：杭州电子科技大学科技馆
Hangzhou Dianzi University; Science & Technology Museum

Final Program of 2nd Sino MOS-AK Workshop is available online
http://www.mos-ak.org/hangzhou_2017/
http://www.xmodtech.cn/Agenda (local link)
Note: 
Above topic and time arrangement sequence could be with tiny variation due to presenter's personal reason
(演讲顺序可能有改变，敬请留意）

Online MOS-AK/Hangzhou Workshop Registration

http://www.xmodtech.cn/registration
(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

WG13062017

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Working Student in Power Management (Intel Munich)

Working Student in Power Management f/m

Job Description: You will be responsible for developing a tool framework to breakdown and manage the power consumption of the Power Management ICs across all projects. The so-called power KPIs Key Performance Indicator are indeed strategic data critical for the competitiveness of battery powered system likes mobiles phones, wearables, IoT devices. You will be part of an enthusiastic and international system engineering team located in Munich and will get in touch locally with several design and validation teams.

Your main tasks in this full time position will be to:
- Setup a new framework to manage the power data in a new tool and environment
- Migrate existing project power consumption specifications and measurements currently in Excel
- Measure and correlate power KPIs on engineering samples in the post-silicon lab.
- Validate current power modelling approach and propose further model optimizations
- Contribute to the reporting and documentation for other teams and management

[read more...]

A Guide to Creating Robust Device Models

Well-Posed Device Models for Electrical Circuit Simulation
A Guide to Creating Robust Device Models
A. Gokcen Mahmutoglu, Tianshi Wang, Archit Gupta and Jaijeet Roychowdhury
March 25, 2017

Synopsis: This document provides guidelines for creating computational device models that work well in simulation. We build our discussion around the mathematical notion of “well-posedness”. We show that the requirements for a model to be well-posed stem from the internal working mechanisms of simulators. Therefore, our main aim is to provide insight into the numerical procedures used by simulators in order to help model developers avoid ill-posedness issues. We start our discussion with an example that shows how an ill-posed Verilog-A model can produce different simulation results in different simulators. We then provide a step-by-step simulation case study. In this case study, we illustrate the role of device models in simulations by examining the steps a simulator goes through, from taking a netlist as input to producing a simulation result as output. Finally, we distill our discussion in a functional definition of a well-posed model. As an extension to our theoretical discussion, we also provide practical guidelines that should be followed by Verilog-A models in order to avoid ill-posedness issues.

This document is published as a part of the Nano-Engineered Electronic Device Simulation (NEEDS) initiative. NEEDS is an NSF-funded initiative whose charter includes the development of tools and techniques for the production of high-quality device models¹:

“NEEDS has a vision for a new era of electronics that couples the power of billion-transistor CMOS technology with the new capabilities of emerging nano-devices and a charter to create high-quality models and a complete development environment that enables a community of compact model developers.

NEEDS Team: Purdue, MIT, UC Berkeley, and Stanford.”

¹For more information about NEEDS please visit https://nanohub.org/groups/needs/
https://nanohub.org/resources/26200/download/well-posed_device_models-29453e4.pdf

[mos-ak] [C4P] IJHSES / MOS-AK Special Issue

The IJHSES Call for Papers

Special Issue on Advances in the Compact/SPICE Modeling

and its Verilog-A Standardization

Compact/SPICE models for circuit level simulation are essential element of supporting CAD/EDA tools for advanced integrated circuit designs. Rapid mainstream CMOS technology expansion and its scaling into the nanometer regime demands development of a fully physical as well as technology predictive compact/SPICE models for circuit simulation which provides adequate, full range DC, AC, RF, and noise characteristics and its geometry, bias, temperature scaling. These tasks becomes a major R&D challenge. Fast new technology nodes developments also impose new challenges on the compact/SPICE models maintenance and development as well as on its Verilog-A standardization for the model implementation, validation and dissemination.

Standard, core compact models should include and update noise/mismatch and reliability/variability models as well as proximity effects to adequately model nanoscale devices and technologies including nonclassical MOSFETs, multigate FinFETs and nanowire FETs partially/fully-depleted ultra thin body (UTB) SOI, and thin-film transistors (TFTs). High-frequency, high-voltage high-power, high-temperature devices have been extensively investigated, and their compact models to be reviewed, too. Heterogeneous integration opens a new perspectives to the CMOS platform to integrate different materials (III-V/Ge channel, organic and different source/drain injection mechanisms (Schottky-barrier, tunneling, junctionless FETs, and others) and new nonclassical devices, high GHz/THz range detectors, Bio/Med sensors, actuators, MEMS, among others, to support emerging device in future VLSI, IoT applications and beyond.

Therefore, there is an emerging need for an new special issue to review status, challenge and advancement in the compact/SPICE modeling for nanoscaled and emerging technologies as well as beyond. The IJHSES Editors seek original manuscripts for a special issue on advanced in the Compact/SPICE Modeling and its Verilog-A standardization.

Topics to be covered include the following, but are not limited to:

• Advances in semiconductor technologies and processing

• Compact Modeling (CM) of the electron devices

• Verilog-A language for CM standardization

• New CM techniques and extraction software

• FOSS TCAD/EDA modeling and simulation

• CM of passive, active, sensors and actuators

• Emerging Devices, TFT CMOS and SOI-based memory cells

• Organic, Bio/Med devices/technology modeling

• Microwave, RF device modeling, HV/Power device modeling

• Nanoscale CMOS devices and circuits

• Technology R&D, DFY, DFT and IC Designs

• Foundry/Fabless Interface Strategies

Paper Submission and Review Schedule:

• First call for papers:    April 2017

• Second announcement:    June 2017

• Special Issue Due:    Dec. 2017

IJHSES Editor-in-Chief	Co-Editors-in-Chiefs	Guest Editors
Michael Shur Rensselaer Polytechnic Institute (USA)	Wladek Grabinski MOS-AK Association (EU) Benjamin Iñiguez DEEEA, ETSE, URV (SP)	Jean-Michel Sallese EPFL Lausanne (CH) Daniel Tomaszewski ITE Warsaw (PL)

WG250417

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[mos-ak] [2nd Announcement and Call for Papers] 2nd Sino MOS-AK Workshop in Hangzhou (CN) June 29-30, 2017

2nd Sino MOS-AK Workshop  

  in Hangzhou (CN) June 29-30, 2017
     2nd Announcement and Call for Papers   

 
Together with Prof. LingLing Sun, HangZhou Dianzi University, the honorary MOS-AK workshop chair,  Dr. Min Zhang, XMOD (Shanghai), local workshop coordinator and International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to the 2nd Sino MOS-AK Workshop which will be held at 会议场所：杭州电子科技大学科技馆 Hangzhou Dianzi University Science & Technology Museum on June 29-20, 2017 in Hangzhou (CN).

Planned MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Important Dates:

• Preannouncement - March 2016
  
• Call for Papers - April 24 2017
  
• Final Workshop Program - June. 2017
  
• MOS-AK Workshop - June 29-30, 2017

Venue:

会议场所：杭州电子科技大学科技馆
Hangzhou Dianzi University Science & Technology Museum
Hangzhou (CN)

Topics to be covered include the following among other related to the compact/SPICE modeling :

• Compact Modeling (CM) of the electron devices
  
• Advances in semiconductor technologies and processing
  
• Verilog-A language for CM standardization
  
• New CM techniques and extraction software
  
• Open Source TCAD/EDA modeling and simulation
  
• CM of passive, active, sensors and actuators
  
• Emerging Devices, TFT, CMOS and SOI-based memory cells
  
• Microwave, RF device modeling, high voltage device modeling
  
• Nanoscale CMOS devices and circuits
  
• Technology R&D, DFY, DFT and reliability/ageing IC Designs
  
• Foundry/Fabless Interface Strategies
  

Invited Speakers (tentative list in alphabetic order)

• Eric Leclerc, UMC Foundry (F)
• Ling Li, Chinese Academy of Sciences (CN)
• Helmut Puchner, Cypress Semi (US)
• Paulius Sakalas, TU Dresden (D)
• Pete Zampardi, RFMD (US)
• Thomas Zimmer, Uni. Bordeaux (F)

Online MOS-AK Abstract Submission:
Prospective authors should submit abstract online

Manuscript submission deadline: 29th May 2017 (Monday)
Notification of Acceptance: 5th June 2017 (Monday)
Submission of final manuscript: 19th June 2017 (Monday)

(any related inquiries can be sent to abstrscts@mos-ak.org)

Online Workshop Registration

using online registration form

(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

WG240417

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[mos-ak] [press note] Spring MOS-AK Workshop at DATE Conference in Lausanne, March 31, 2017

 Arbeitskreis Modellierung von Systemen und Parameterextraktion
 Modeling of Systems and Parameter Extraction Working Group
 Spring MOS-AK Workshop at DATE
 Lausanne, March 31, 2017

 The MOS-AK Compact Modeling Association, a global compact/SPICE modeling and Verilog-A standardization forum, held its annual spring workshop as an integral engineering event at the DATE Conference on March 30, 2017 in Lausanne (CH). The event was coorganized by Jean-Michel Sallese, EPFL and its technical program was coordinated by Larry Nagel, OEC (USA) and Andrei Vladimirescu, UCB (USA); ISEP (FR) representing the International MOS-AK Board of R&D Advisers. The workshop was co-sponsored by MPI Corporation (lead sponsor) and Swiss IEEE Section, with technical program promotion provided by the IEEE WiE Group (CH), Eurotraining and NEEDS of nanoHUB.org as well as FOSSEE fossee.in

 

A group of the international academic researchers and modeling engineers attended 12 technical compact modeling presentations covering full development chain form the nanoscaled technologies thru semiconductor devices modeling to advanced IC design support. The MOS-AK speakers have shared their latest perspectives on compact/SPICE modeling and Verilog-A standardization in the dynamically evolving semiconductor industry and academic R&D. 

The event featured advanced technical presentations covering compact model development, implementation, deployment and standardization covering full engineering R&D chain: TCAD/processing, device modeling, transistor level IC design support. These contributions were delivered by leading academic and industrial experts, including: Nicolas Cordero, Tyndall (IE) ASCENT (Nanoelectronics Network) - Open Access to 14nm PDKs; Vadim Kuznetsov, Bauman Moscow TU (RU) The first stable release of Qucs-S and advances in XSPICE model synthesis; Anurag Mangla, ams AG (A) Interactive tool for quick calculation of design oriented MOSFET parameters; Maria-Alexandra Paun, EPFL (CH) Optimal geometry selection for Hall sensors integrated in CMOS technological process; Heinz-Olaf Müller, Plastic Logic (D) Verilog-A model for ferroelectrics in organic electronics; Andrej Rumiantsev, MPI Corp. (TW) New Approach to Reduce Time-to-data when Characterizing Advanced Semiconductor Devices; Mathieu Luisier, ETH Zurich (CH), Physics-based Modeling of Nano-Devices: Requirements and Examples; Felix Salfelder, University of Leeds (UK) Semiconductor Device Compact Modelling with Ageing Effects; Theodor Hillebrand, University of Bremen (D) Unified charge-based Transistor Model including Degradation Mechanisms; Catherine Dehollain, EPFL (CH) Design trade-off between remote power and data communication for remotely powered sensor networks; Sandro Carrara, EPFL (CH) Bio/Nano/CMOS interfaces for Ultrasensitive Memristive Biosensors; Matthias Bucher; TUC (GR), giving an EKV3 model update. The presentations are available online for download at <http://www.mos-ak.org/lausanne_2017>. Selected best presentation will be recommended for further publication in the IJHSES.

 

The MOS-AK Modeling Working Group has various deliverables and initiatives including a book entitled "Open Source CAD Tools for Compact Modeling" and an open Verilog-A directory with models and supporting CAD software. The MOS-AK Association plans to continue its standardization efforts by organizing additional compact modeling meetings, workshops and courses in Europe, USA, India and China throughout 2017/2018 including:

* 2nd Sino MOS-AK Workshop in Hangzhou (June 29-30, 2017)

* 15th MOS-AK ESSDERC/ESSCIRC Workshop in Leuven (Sept.11, 2017)

* 10th International MOS-AK Workshop in Silicon Valley; Dec. 2017

* Spring MOS-AK Workshop Strasbourg (F) March 2018

 

About MOS-AK Association:

MOS-AK, an international compact modeling association primarily focused in Europe, to enable international compact modeling R&D exchange in the North/Latin Americas, EMEA and Asia/Pacific Regions. The MOS-AK Modeling Working Group plays a central role in developing a common language among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact/SPICE modeling and its Verilog-A standardization and related CAD/EDA tools for the compact models development, validation/implementation and distribution. For more information please visit: mos-ak.org

About MPI Corporation:

Founded in 1995 and headquartered in Hsinchu, Taiwan, MPI Corporation is a global technology leader in Semiconductor, Light Emitting Diode (LED), Photo Detectors, Lasers, Materials Research, Aerospace, Automotive, Fiber Optic, Electronic Components and more. MPI's four main business sectors include Probe Card, Photonics Automation, Advanced Semiconductor Test and Thermal Divisions. MPI products range from various advanced probe card technologies, probers, testers, material handlers, inspection and thermal air systems. Many of these products are accompanied by state-of-the-art Calibration and Test &amp; Measurement software suites. The diversification of product portfolio and industries allows a healthy environment for employee growth and retention. Cross pollination of product technologies allows each new innovation to provide differentiation in areas that are meaningful to our precious customer base. For more information please visit: mpi-corporation.com

WG230417

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2017 National Academy of Inventors Fellow Induction

National Academy of Inventors Fellow Induction

Chenming Hu

TSMC Distinguished Professor Emeritus at UC Berkeley

Among all NAI Fellows there are now 94 presidents and senior leaders of research universities and non-profit research institutes, 382 members of the National Academies of Sciences, Engineering, and Medicine, 31 inductees of the National Inventors Hall of Fame, 45 recipients of the U.S. National Medal of Technology and Innovation and U.S. National Medal of Science, 28 Nobel Laureates, 216 AAAS Fellows, 126 IEEE Fellows, and 116 Fellows of the American Academy of Arts & Sciences, among other awards and distinctions. [read more...]

2017 IEEE Andrew S. Grove Award

Prof. Sorin Cristoloveanu,  CNRS at IMEP-LAHC

2017 IEEE Andrew S. Grove Award Recipient

“For contributions to silicon-on-insulator technology and thin body devices”

A visionary device physics researcher, Sorin Cristoloveanu saw the potential that silicon-on-insulator (SOI) technology held for the semiconductor industry in producing competitive microelectronics components with improved performance when others considered it a niche field. As early as 1976, he discovered key mechanisms of thin-body devices that have led to the development of transistors from the simplest (zero gate) to the most complicated (four gates). Among several concepts unveiled by his group, the demonstration during the 1980s that volume inversion occurs in all nano-body devices was revolutionary at the time and helped drive research that led to double-gate transistors and today’s tri-gate FinFET devices. His Pseudo-MOSFET method developed in 1992 has become an industry standard for wafer monitoring without having to actually fabricate devices. More recently, Cristoloveanu’s SOI expertise has led to innovative devices for low-power memory and sharp-switching circuits. An IEEE Fellow, Cristoloveanu is the director of research at CNRS at IMEP-LAHC, Grenoble, France [read more...]

[paper] Artificial neural network design for compact modeling of generic transistors

Artificial neural network design for compact modeling of generic transistors

(J Comput Electron; pp. 1-8;  2017)

Lining Zhang and Mansun Chan

Department of ECE, Hong Kong University of Science and
Technology, Kowloon, Hong Kong

Abstract: A methodology to develop artificial neural network (ANN) models to quickly incorporate the characteristics of emerging devices for circuit simulation is described in this work. To improve the model accuracy, a current and voltage data preprocessing scheme is proposed to derive a minimum dataset to train the ANN model with sufficient accuracy. To select a proper network size, four guidelines are developed from the principles of two-layer network. With that, a reference ANN size is proposed as a generic three-terminal transistor model. The ANN model formulated using the proposed approach has been verified by physical device data. Both the device and circuit-level tests show that the ANN model can reproduce and predict various device and circuits with high accuracy [read more...]

(Published online April 9, 2017 http://dx.doi.org/10.1007/s10825-017-0984-9)

Starting Framework of the IRDS Roadmap

IEEE has announced the next milestone phase in the development of the International Roadmap for Devices and Systems (IRDS), an IEEE Standards Association (IEEE-SA) Industry Connections (IC) Program sponsored by the IEEE Rebooting Computing (IEEE RC) Initiative with the launch of a series of nine white papers that reinforce the initiative’s core mission and vision for the future of the computing industry. The white papers also identify industry challenges and solutions that guide and support future roadmaps created by IRDS [read more...]

The series of white papers delivers the starting framework of the IRDS roadmap - and through the sponsorship of IEEE RC—will inform the various roadmap teams in the broader task of mapping the devices’ and systems’ ecosystem:

• Applications Benchmarking
• More Moore
• Beyond CMOS (Emerging Research Devices)
• Outside System Connectivity
• Factory Integration
• Metrology
• Environment, Safety, and Health
• Yield Enhancement
• System and Architecture

The IRDS leadership team hosted a winter workshop and kick-off meeting at the Georgia Institute of Technology on 1-2 December 2016. Key discoveries from the workshop included the international focus teams’ plans and focus topics for the 2017 roadmap, top-level needs and challenges, and linkages among the teams. Additionally, the IRDS leadership invited presentations from the European and Japanese roadmap initiatives. This resulted in the 2017 IRDS global membership expanding to include team members from the “NanoElectronics Roadmap for Europe: Identification and Dissemination” (NEREID) sponsored by the European Semiconductor Industry Association (ESIA), and the “Systems and Design Roadmap of Japan” (SDRJ) sponsored by the Japan Society of Applied Physics (JSAP).

The IRDS team and its supporters will convene 1-3 April 2017 in Monterey, California, for the Spring IRDS Workshop, which is part of the 2017 IEEE International Reliability Physics Symposium (IRPS). The team will meet again for the Fall IRDS Conference in partnership with the 2017 IEEE International Conference on Rebooting Computing (ICRC) scheduled for 6-7 November 2017 in Washington, D.C. More information on both events can be found here.

IEEE RC is a program of IEEE Future Directions, designed to develop and share educational tools, events, and content for emerging technologies [read more...]

NIST Digital Library of Mathematical Functions

Project News

• 2016-12-21 DLMF Update; Version 1.0.14
• 2016-09-16 DLMF Update; Version 1.0.13
• 2016-09-09 DLMF Update; Version 1.0.12
• 2016-06-08 Future expansion
• More news

---

Foreword Preface Mathematical Introduction 1 Algebraic and Analytic Methods 2 Asymptotic Approximations 3 Numerical Methods 4 Elementary Functions 5 Gamma Function 6 Exponential, Logarithmic, Sine, and Cosine Integrals 7 Error Functions, Dawson’s and Fresnel Integrals 8 Incomplete Gamma and Related Functions 9 Airy and Related Functions 10 Bessel Functions 11 Struve and Related Functions 12 Parabolic Cylinder Functions 13 Confluent Hypergeometric Functions 14 Legendre and Related Functions 15 Hypergeometric Function 16 Generalized Hypergeometric Functions & Meijer G-Function 17 q-Hypergeometric and Related Functions 18 Orthogonal Polynomials 19 Elliptic Integrals

20 Theta Functions 21 Multidimensional Theta Functions 22 Jacobian Elliptic Functions 23 Weierstrass Elliptic and Modular Functions 24 Bernoulli and Euler Polynomials 25 Zeta and Related Functions 26 Combinatorial Analysis 27 Functions of Number Theory 28 Mathieu Functions and Hill’s Equation 29 Lamé Functions 30 Spheroidal Wave Functions 31 Heun Functions 32 Painlevé Transcendents 33 Coulomb Functions 34 3j, 6j, 9j Symbols 35 Functions of Matrix Argument 36 Integrals with Coalescing Saddles Bibliography Index Notations List of Figures List of Tables Software Errata

[paper] Pulsed I-V on TFETs: Modeling and Measurements

Pulsed I-V on TFETs: Modeling and Measurements
Quentin Smets, Anne Verhulst, Ji-Hong Kim, Jason P. Campbell, David Nminibapiel, Dmitry Veksler, Pragya Shrestha, Rahul Pandey, Eddy Simoen, David Gundlach, Curt Richter, Kin P. Cheung, Suman Datta, Anda Mocuta, Nadine Collaert, Aaron V.-Y. Thean, and Marc M. Heyns
in IEEE Transactions on Electron Devices, vol. 64, no. 4, pp. 1489-1497, April 2017
doi: 10.1109/TED.2017.2670660

Abstract: Most experimental reports of tunneling field-effect transistors show defect-related performance degradation. Charging of oxide traps causes Fermi-level pinning, and Shockley–Read–Hall (SRH)/trap-assisted tunneling (TAT) cause unwanted leakage current. In this paper, we study these degradation mechanisms using the pulsed I-V technique. Our simulations show pulsed I-V can fully suppress oxide trap charging, unlike SRH and TAT. We discuss several circuit-related pitfalls, and we demonstrate improved transfer characteristics by suppressing oxide trap charging using cryogenic pulsed I-V [read more...]

[mos-ak] [paper submission] Device and Circuit Compact Modeling TRACK4 at ESSDERC

Dear Compact Modeling Experts,

I would like to draw your attention to newly opened Device and Circuit Compact Modeling TRACK4 at ESSDERC. I was assigned to chair the track 4 with a group of the international reviewers. The new tract will cover a broad range of the compact modeling and its Verilog-A standardization topics (see below). I hope you will find these topic matching your current scientific work and R&D activities and you will eventually submit your conference paper for our new Device and Circuit Compact Modeling TRACK4 at ESSDERC.

Papers must not exceed four A4 pages with all illustrations and references included. All submissions must be received by 10 April, 2017. After selection of papers, the authors will be informed about the decision of the Technical Program Committee by e-mail by June 2, 2017. At the same time, the complete program will be published on the ESSDERC/ESSCIRC website.

I will be glad if you could also proactively promote our Device and Circuit Compact Modeling TRACK4 and also motivate and invite other compact modeling researchers and engineers to also submit their R&D scientific conference contributions. Please distribute my open invitation to all experts in your region.

Already now, I am looking forward to receive your conference submission and then meeting you at ESSDERC in Leuven.

-- thanks in advance -- wladek;
--
ESSDERC TRACK4: Device and Circuit Compact Modeling
TPC <http://www.esscirc-essderc2017.org/essderc-technical-program-committee>
Topics:<http://www.esscirc-essderc2017.org/essderc-call-for-papers>
Compact/SPICE modeling of electronic, optical, organic, and hybrid devices and their IC implementation and interconnection. Topics include compact/SPICE models and its Verilog-A standardization of the semiconductor devices (including Bio/Med sensors, MEMS, Microwave, RF, High voltage and Power), parameter extraction, compact models for emerging technologies and novel devices, performance evaluation, reliability, variability, and open source benchmarking/implementation methodologies. Modeling of interactions between process, device, and circuit design as well as Foundry/Fabless Interface Strategies.
---

WG160317

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Qucs Roadmap

The QUCS Roadmap should serve as base to track the status of each action point. Enhancements can be handled in two ways:

• For simpler enhancements an issue/bug ticket shall be created and referenced back here. The pertinent discussion and documentation should be done on the body of each ticket.
• For more complex enhancements a Qucs Enhancement Proposal should be created and reference back here.

The open action points can be further categorized concerning the difficulty or amount of work as (Easy, Medium, Hard) and priority (0-3, 0 is the highest). See the Port to Qt4 / Qt5 for an example. Tickets will be tracked individually and assigned to milestones leading to stable releases.

Stage 1 - Simple GUI and simulator  

Stage 2 - Implementation of powerful circuit analysis tools

Stage 3 - Support for more design and synthesis tools  

Stage 4 - Implementation of industry standard device models

Stage 5 - Design realization, production, verification

Read more about QUCS Roadmap

Bio-SPICE

Bio-SPICE: Biological Simulation Program for Intra- and Inter-Cellular Evaluation

 

Bio-SPICE, an open source framework and software toolset for Systems Biology, is intended to assist biological researchers in the modeling and simulation of spatio-temporal processes in living cells. In addition, our goal is to develop and serve a user community committed to using, extending, and exploiting these tools to further our knowledge of biological processes.

In collaboration with other Bio-SPICE, Community members, we will develop, license, distribute, and maintain a comprehensive software environment that integrates a suite of analytical, simulation, and visualization tools and services to aid biological researchers engaged in building computable descriptions of cellular functions. From disparate data analysis and information mining to experimental validation of computational models of cell systems, our environment will offer a comprehensive substrate for efficient research, collaboration, and publication.

Mission
Bio-SPICE, is intended for modeling and simulation of spatio-temporal processes in living cells. The goals of Bio-SPICE, are to support discovery through:

1. Developing computational and mathematical models of bio-molecular systems in cells capturing the nature of gene-protein interactions
2. Developing tools that can rapidly incorporate relevant experimental data and knowledge known in the literature to build models of pathways, networks, and spatial processes
3. Developing simulation tools for the dynamic analysis of bio-molecular systems
4. Creating an extensible framework for easy insertion of models and their refinement, as well as customization to specific mechanisms

In addition, our goal is to develop and serve a user community committed to using, extending, and exploiting these tools to further our knowledge of biological processes. In collaboration with other Bio-SPICE Community members, we will develop, license, distribute, and maintain a comprehensive software environment that integrates a suite of analytical, simulation, and visualization tools and services to aid biological researchers engaged in building computable descriptions of cellular functions. From disparate data analysis and information mining to experimental validation of computational models of cell systems, our environment will offer a comprehensive substrate for efficient research, collaboration, and publication [read more...]

[paper] III-V Channel Double Gate FETs

Compact Modeling of Charge, Capacitance, and Drain Current
in III-V Channel Double Gate FETs

C. Yadav; M. Agrawal; A. Agarwal; Y. S. Chauhan

in IEEE Transactions on Nanotechnology , vol.PP, no.99, pp.1-1
doi: 10.1109/TNANO.2017.2669092

Abstract: In this paper, we present a surface potential based compact modeling of terminal charge, terminal capacitance, and drain current for III-V channel double gate field effect transistor (DGFET) including the effect of conduction band nonparabolicity. The proposed model is developed accounting for the 2-D density of states and includes the effect of quantum capacitance associated with the low density of states channel material. In addition, model incorporates contribution of the first two subbands and efficiently captures the step like behavior appearing in the gate capacitance and trans-conductance with population of the higher sub-bands. The behavior of bias dependent terminal capacitances and drain current are verified with the numerical simulation data of InGaAs channel DGFET and shows a close agreement with the simulation data [read more...]