Thursday, March 16, 2017

[mos-ak] [paper submission] Device and Circuit Compact Modeling TRACK4 at ESSDERC

Dear Compact Modeling Experts,
I would like to draw your attention to newly opened Device and Circuit Compact Modeling TRACK4 at ESSDERC. I was assigned to chair the track 4 with a group of the international reviewers. The new tract will cover a broad range of the compact modeling and its Verilog-A standardization topics (see below). I hope you will find these topic matching your current scientific work and R&D activities and you will eventually submit your conference paper for our new Device and Circuit Compact Modeling TRACK4 at ESSDERC.

Papers must not exceed four A4 pages with all illustrations and references included. All submissions must be received by 10 April, 2017. After selection of papers, the authors will be informed about the decision of the Technical Program Committee by e-mail by June 2, 2017. At the same time, the complete program will be published on the ESSDERC/ESSCIRC website.

I will be glad if you could also proactively promote our Device and Circuit Compact Modeling TRACK4 and also motivate and invite other compact modeling researchers and engineers to also submit their R&D scientific conference contributions. Please distribute my open invitation to all experts in your region.

Already now, I am looking forward to receive your conference submission and then meeting you at ESSDERC in Leuven.

-- thanks in advance -- wladek;
ESSDERC TRACK4: Device and Circuit Compact Modeling
TPC <>
Compact/SPICE modeling of electronic, optical, organic, and hybrid devices and their IC implementation and interconnection. Topics include compact/SPICE models and its Verilog-A standardization of the semiconductor devices (including Bio/Med sensors, MEMS, Microwave, RF, High voltage and Power), parameter extraction, compact models for emerging technologies and novel devices, performance evaluation, reliability, variability, and open source benchmarking/implementation methodologies. Modeling of interactions between process, device, and circuit design as well as Foundry/Fabless Interface Strategies.

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