Compact Modeling of Charge, Capacitance, and Drain Current
in III-V Channel Double Gate FETs
in III-V Channel Double Gate FETs
C. Yadav; M. Agrawal; A. Agarwal; Y. S. Chauhan
in IEEE Transactions on Nanotechnology , vol.PP, no.99, pp.1-1
doi: 10.1109/TNANO.2017.2669092
doi: 10.1109/TNANO.2017.2669092
Abstract:
In this paper, we present a surface potential based compact modeling of
terminal charge, terminal capacitance, and drain current for III-V
channel double gate field effect transistor (DGFET) including the effect
of conduction band nonparabolicity. The proposed model is developed
accounting for the 2-D density of states and includes the effect of
quantum capacitance associated with the low density of states channel
material. In addition, model incorporates contribution of the first two
subbands and efficiently captures the step like behavior appearing in
the gate capacitance and trans-conductance with population of the higher
sub-bands. The behavior of bias dependent terminal capacitances and
drain current are verified with the numerical simulation data of InGaAs
channel DGFET and shows a close agreement with the simulation data [read more...]
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