Tuesday, April 25, 2017

[mos-ak] [C4P] IJHSES / MOS-AK Special Issue

The IJHSES Call for Papers

Special Issue on Advances in the Compact/SPICE Modeling

and its Verilog-A Standardization

Compact/SPICE models for circuit level simulation are essential element of supporting CAD/EDA tools for advanced integrated circuit designs. Rapid mainstream CMOS technology expansion and its scaling into the nanometer regime demands development of a fully physical as well as technology predictive compact/SPICE models for circuit simulation which provides adequate, full range DC, AC, RF, and noise characteristics and its geometry, bias, temperature scaling. These tasks becomes a major R&D challenge. Fast new technology nodes developments also impose new challenges on the compact/SPICE models maintenance and development as well as on its Verilog-A standardization for the model implementation, validation and dissemination.

Standard, core compact models should include and update noise/mismatch and reliability/variability models as well as proximity effects to adequately model nanoscale devices and technologies including nonclassical MOSFETs, multigate FinFETs and nanowire FETs partially/fully-depleted ultra thin body (UTB) SOI, and thin-film transistors (TFTs). High-frequency, high-voltage high-power, high-temperature devices have been extensively investigated, and their compact models to be reviewed, too. Heterogeneous integration opens a new perspectives to the CMOS platform to integrate different materials (III-V/Ge channel, organic and different source/drain injection mechanisms (Schottky-barrier, tunneling, junctionless FETs, and others) and new nonclassical devices, high GHz/THz range detectors, Bio/Med sensors, actuators, MEMS, among others, to support emerging device in future VLSI, IoT applications and beyond.

Therefore, there is an emerging need for an new special issue to review status, challenge and advancement in the compact/SPICE modeling for nanoscaled and emerging technologies as well as beyond. The IJHSES Editors seek original manuscripts for a special issue on advanced in the Compact/SPICE Modeling and its Verilog-A standardization.

Topics to be covered include the following, but are not limited to:

  • Advances in semiconductor technologies and processing

  • Compact Modeling (CM) of the electron devices

  • Verilog-A language for CM standardization

  • New CM techniques and extraction software

  • FOSS TCAD/EDA modeling and simulation

  • CM of passive, active, sensors and actuators

  • Emerging Devices, TFT CMOS and SOI-based memory cells

  • Organic, Bio/Med devices/technology modeling

  • Microwave, RF device modeling, HV/Power device modeling

  • Nanoscale CMOS devices and circuits

  • Technology R&D, DFY, DFT and IC Designs

  • Foundry/Fabless Interface Strategies

Paper Submission and Review Schedule:

  • First call for papers:    April 2017

  • Second announcement:    June 2017

  • Special Issue Due:    Dec. 2017

IJHSES Editor-in-Chief


Guest Editors

Michael Shur

Rensselaer Polytechnic Institute (USA)

Wladek Grabinski

MOS-AK Association (EU)

Benjamin IƱiguez


Jean-Michel Sallese

EPFL Lausanne (CH)

Daniel Tomaszewski

ITE Warsaw (PL)


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