[paper] A Compact Model of Gate Capacitance in Ballistic GAA-CNFET

A. Dixit, N. Gupta

A Compact Model of Gate Capacitance 

in Ballistic Gate-all-around Carbon Nanotube Field Effect Transistors 

IJE TRANSACTIONS A: Basics Vol. 34, No. 7, (July 2021) 1718-1724 

DOI: 10.5829/ije.2021.34.07a.16

* Nanomaterial Device Laboratory, Department of Electrical and Electronics Engineering,
Birla Institute of Technology and Science, Pilani, Rajasthan, India

Abstract: This paper presents a one-dimensional analytical model for calculating gate capacitance in Gate-All-Around Carbon Nanotube Field Effect Transistor (GAA-CNFET) using electrostatic approach. The proposed model is inspired by the fact that quantum capacitance appears for the Carbon Nanotube (CNT) which has a low density of states. The gate capacitance is a series combination of dielectric capacitance and quantum capacitance. The model so obtained depends on the density of states (DOS), surface potential of CNT, gate voltage and diameter of CNT. The quantum capacitance obtained using developed analytical model is 2.84 pF/cm for (19, 0) CNT, which is very close to the reported value 2.54 pF/cm. While, the gate capacitance comes out to be 24.3×10-2 pF/cm. Further, the effects of dielectric thickness and diameter of CNT on the gate capacitance are also analyzed. It was found that as we reduce the thickness of dielectric layer, the gate capacitance increases very marginally, which provides better gate control upon the channel. The close match between the calculated and simulated results confirms the validity of the proposed model.

Fig. Schematic view of CNFET for modelling gate capacitance (a) front view (b) side view

Acknowledgements: Authors acknowledge the financial support of Defence Research and Development Organisation (DRDO), Govt. of India [ERIP/ER/DGMED&OS/990416502/ M/01/1657] and Nanomaterial device laboratory, BITS Pilani for carrying research out work reported this paper.

[paper] III-V Channel Double Gate FETs

Compact Modeling of Charge, Capacitance, and Drain Current
in III-V Channel Double Gate FETs

C. Yadav; M. Agrawal; A. Agarwal; Y. S. Chauhan

in IEEE Transactions on Nanotechnology , vol.PP, no.99, pp.1-1
doi: 10.1109/TNANO.2017.2669092

Abstract: In this paper, we present a surface potential based compact modeling of terminal charge, terminal capacitance, and drain current for III-V channel double gate field effect transistor (DGFET) including the effect of conduction band nonparabolicity. The proposed model is developed accounting for the 2-D density of states and includes the effect of quantum capacitance associated with the low density of states channel material. In addition, model incorporates contribution of the first two subbands and efficiently captures the step like behavior appearing in the gate capacitance and trans-conductance with population of the higher sub-bands. The behavior of bias dependent terminal capacitances and drain current are verified with the numerical simulation data of InGaAs channel DGFET and shows a close agreement with the simulation data [read more...]