LibreCAD is a fully comprehensive 2D CAD application that you can download and install for free. LibreCAD is an Open Source community-driven project: development is open to new talent and new ideas, and our software is tested and used daily by a large and devoted user community; you, too, can get involved and influence its future development. LibreCAD has GPLv2 public license – you can use it, customize it, hack it and copy it with free user support and developer support from our active worldwide community and our experienced developer team. There is a large base of satisfied LibreCAD users worldwide, and it is available in more than 20 languages and for all major operating systems, including Microsoft Windows, Mac OS X and Linux, including Debian, Ubuntu, Fedora, Mandriva, Suse, etc.
Feb 24, 2016
LibreCAD: Call for Your POTM Vote
The vote for April 2016 Community Choice SourceForge Project of the Month is now available, and will run until March 15, 2016 12:00 UTC. Here is one of the candidates:
Feb 22, 2016
Alliance: FOSS VLSI/CAD System
Alliance is a complete set of free cad tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools. A complete set of portable CMOS libraries is provided. Alliance is the result of a twelve year effort spent at SoC department of LIP6 laboratory of the Pierre & Marie Curie University (Paris VI, France). Alliance has been used for research projects such as the 875 000 transistors StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL Router.
Alliance VLSI CAD System is free software. Binaries, source code and cells libraries are freely available under the GNU General Public License (GPL). You are welcome to use the software package even for commercial designs without any fee. You are kindly requested to mention: "Designed with Alliance © LIP6, Université Pierre et Marie Curie".
ICs Designed with Alliance
- Smartlabs/Smarthome designed a complete circuit in the XFAB XH035 technology (2014).
- Tokai University (Shimizu Lab) designed the SNX, a 16 bits processor in the ROHM 0.18µm (2010).
- Improved Standard Cell libraries and documentation on how to design them, by Graham Petley: VLSI Technology
- A book presenting Alliance in depth: Introduction to VLSI CMOS Circuits design by Carlos SilvaCardenas, Takeo Yoshida & Alberto Palacios Pawlovsky.
- For Spanish readers, a set of tutorials made by Miguel Eduardo Flores Gomez from Don Bosco University: Tutorial de Alliance
Feb 19, 2016
[video] How to Model RF Passive Devices: Spiral Inductors
How to Model RF Passive Devices: Spiral Inductors
With increasing operating frequencies, the modeling of passive components becomes increasingly important, and there exist no ready-to-use models for inductors, resistors, capacitors etc. Based on the other video of this fundamental device modeling series, (How to Model RF Capacitors and Resistors), this video extends the topic to modeling RF Spiral Inductors. It explains how to develop a Spice model based on verified S-Parameter measurements. Applying an easy to follow, step by step procedure, the video walks you through the entire modeling flow for on-wafer inductors, using the Keysight Measurement and Modeling Software IC-CAP.
The IC-CAP project (modeling spiral inductors with and without metal-1 shielding) can be downloaded together with a detailed pdf explaining the steps demonstrated in the video.
http://www.keysight.com/find/eesof-how-to-model-spiral-inductors
Published on Feb 11, 2016
Feb 18, 2016
Tin Oxide: The First Stable p-type #2D #Semiconductor Material https://t.co/mKQ9vHsbrJ #papers #feedly
Tin Oxide: The First Stable p-type #2D #Semiconductor Material https://t.co/mKQ9vHsbrJ #papers #feedly
— Wladek Grabinski (@wladek60) February 18, 2016
from Twitter https://twitter.com/wladek60
February 18, 2016 at 07:59AM
via IFTTT
Feb 10, 2016
#TFETs may #challenge MOSFETs https://t.co/9tyWFYJprp #cad #feedly #papers
#TFETs may #challenge MOSFETs https://t.co/9tyWFYJprp #cad #feedly #papers
— Wladek Grabinski (@wladek60) February 10, 2016
from Twitter https://twitter.com/wladek60
February 10, 2016 at 12:46PM
via IFTTT
Obama makes risky bid to increase #science #spending https://t.co/ckzMvs97eb #papers #feedly
Obama makes risky bid to increase #science #spending https://t.co/ckzMvs97eb #papers #feedly
— Wladek Grabinski (@wladek60) February 10, 2016
from Twitter https://twitter.com/wladek60
February 10, 2016 at 07:57AM
via IFTTT
Feb 9, 2016
MIXDES 2016 Paper Submission Deadline
MIXDES Paper Submission Deadline
(March 1st, 2016)
---------- Forwarded message ----------From: MIXDES 2016 Organizing Committee
Dear Colleagues,
I would like to kindly remind you that paper submission for MIXDES 2016 Conference has been already opened. The deadline for regular paper submission is March 1st, 2016, so I encourage you to register your papers. The instruction for paper preparation is available online. Please note that the paper format and content may be still updated up to Final Paper Version deadline (May 31st, 2016).
www.mixdes.org.
If you have any questions please do not hesitate to contact me.
Hoping to see you in Lodz,
Mariusz Orlikowski
Secretary of the 23rd International Conference
"Mixed Design of Integrated Circuits and Systems"
MIXDES 2016
http://www.mixdes.org
Feb 7, 2016
Device to GDSII for IC Design Training
Hands on Training Program on “Device to GDSII for IC Design”
on 22-27 Feb 2016
Organized by VLSI Division of School of Electronics Engineering
Vellore Institute of Technology, Near Katpadi Rd Vellore, Tamil Nadu - 632014
The relentless march fast of the CMOS has slowed down and the semiconductor industry is looking for novel and innovative devices. Many novel devices are being explored currently. TCAD and Cadence tool allows us to generate new structures, circuits and analyze its performance. Unlike other circuit simulators, TCAD and Cadence needs a special training. This hands on training addresses this gap.
Target Audience: Faculty, students and research scholars from various engineering colleges of India. The number of participants is limited to 40.
Topics to ďe addressed:
Using TCAD:
- Structure Creation, Simulation and Device Simulation
- Process Simulation
- Multi-gate Transistors
- Radiation study on devices and circuits
Using Cadence:
- RTL Design and Simulation
- Synthesis and low power synthesis Using RTL Compiler
- Physical aware synthesis and DFT
- Block and Top Level P&R Using SOC Encounter
- STA Using Timing Engine
Advanced Test Engineering Course
Barcelona, Spain
February 15-16, 2016 (2 days)
The course will highlight board and system-level manufacturing test and supportability issues. In order to achieve the unambiguous isolation of the faulty circuits, testability has to be assessed at the design stage – often before the circuit details are known. We will examine how this can be achieved using diagnostic assessment and modeling techniques. Finally, the course will evaluate the value of DFT and BIST at all levels of assembly from an economic perspective. You will leave the course with a thorough understanding of techniques, and guidelines you can put to use right away to manage automatic test and ATE at your company. The DFT and BIST methods will profit both manufacturing and support, while at the same time greatly improve the quality of units under test UUTs.
Who should attend: This course is not only of interest to designers and test engineers, but it will also be of great value to reliability, logistics, quality and manufacturing engineers. Managers concerned with testability and BIST techniques as part of DFX, as well as those with general interest of IEEE and military standards in DFT should find this course a great value.
Instructor: Louis Y. Ungar; Details and Availability [read more...]
Simulating the World’s Smallest Integrated Switch
This visualization from CSCS in Switzerland shows the world’s smallest integrated switch.
The switch is based on the voltage-induced displacement of one or more silver atoms in the narrow gap between a silver and a platinum plate.
Researchers working under Juerg Leuthold, Professor of Photonics and Communications at ETH Zurich, have created the world’s smallest integrated optical switch. Applying a small voltage causes an atom to relocate, turning the switch on or off. ETH Professor Mathieu Luisier, who participated in this study, simulated the system using Piz Daint Supercomputer. The component operates at the level of individual atoms. The team’s latest development was recently presented in the journal Nano Letters.
Feb 5, 2016
gEDA Edinburgh meetup - Saturday 6th February 2016
gEDA Edinburgh Meetup
Saturday 6th February 2016
---------- Fwd message ----------
From: "Peter TB Brett"
Date: 3 Feb 2016 13:57
Subject: gEDA Edinburgh meetup - Saturday 6th February 2016
----------
From: "Peter TB Brett"
Date: 3 Feb 2016 13:57
Subject: gEDA Edinburgh meetup - Saturday 6th February 2016
----------
Hi all,
There will be a UK meet-up and hack day this weekend.
Sorry for the short notice. It's on Saturday so as not to conflict with the PCB hack day on Sunday.
Peter Clifton and I will both be there, and everybody else who can attend for all or some of the day will be welcome. We'll also be using the #geda channel on irc.oftc.net
If you use or develop free and open source system (FOSS) design and simulation software, you'd be welcome to attend!
Peter
There will be a UK meet-up and hack day this weekend.
- Edinburgh, UK
Saturday 6th of February
Sorry for the short notice. It's on Saturday so as not to conflict with the PCB hack day on Sunday.
Peter Clifton and I will both be there, and everybody else who can attend for all or some of the day will be welcome. We'll also be using the #geda channel on irc.oftc.net
If you use or develop free and open source system (FOSS) design and simulation software, you'd be welcome to attend!
Peter
---------- End of Fwd message ----------
Free Computational Electromagnetic Modeling Codes
The software in this list is either free or available at a nominal charge and can be downloaded over the internet. Some of the codes require the user to register with the distributor's web site. If you are familiar with other free EM modeling software that that should be added to this list, please send the name of the software, a hypertext link, and a brief description to CVEL-L@clemson.edu.
This page has been translated into Italian here, Serbo-Croatian here, Slovakian here, Swedish here and Polish here and here.
This page has been translated into Italian here, Serbo-Croatian here, Slovakian here, Swedish here and Polish here and here.
(Page last update: December 14, 2015 )
ASAP - Antenna Scatterers Analysis Program
AtaiTec Free 2D Field Solver
ATLC - Arbitrary Transmission Line Calculator
ATLC2 - Arbitrary Transmission Line Calculator 2
emAnalyze
EMAP
EMCoS Antenna VLab SV
EM Explorer
emGine Environment
ERMES
FastCap and FastHenry
FEKO LITE
FEMM - Finite Element Method Magnetics
gprMax
MagNet (Infolytica)
MMANA-GAL (basic version)
MEEP
MMTL
Multiple Multipole (MMP) Algorithms
NEC2
newFasant (student version)
openEMS
pdnMesh
Puma-EM
Qsci
Radia
SATE Static Field Analysis Toolkit (Educational)
Students' QuickField
Sonnet Lite
Trace Analyzer
AtaiTec Free 2D Field Solver
ATLC - Arbitrary Transmission Line Calculator
ATLC2 - Arbitrary Transmission Line Calculator 2
emAnalyze
EMAP
EMCoS Antenna VLab SV
EM Explorer
emGine Environment
ERMES
FastCap and FastHenry
FEKO LITE
FEMM - Finite Element Method Magnetics
gprMax
MagNet (Infolytica)
MMANA-GAL (basic version)
MEEP
MMTL
Multiple Multipole (MMP) Algorithms
NEC2
newFasant (student version)
openEMS
pdnMesh
Puma-EM
Qsci
Radia
SATE Static Field Analysis Toolkit (Educational)
Students' QuickField
Sonnet Lite
Trace Analyzer
Feb 4, 2016
Funding the Costs of Open Access Publishing
The EC FP7 Post-Grant Open Access Pilot:
Funding the Costs of Open Access Publishing
This blogpost was aimed to provide a background to the discussion on Open Access held at the now cancelled Nov 26-27th Euraxess-Voice of the Researchers conference in Brussels. The barbarians may have succeeded in sabotaging a unique opportunity for civilized discussion on how to achieve progress through research, but they will not stop our building the absolute opposite to what they represent.
A new funding initiative has been launched by the European Commission earlier this year in order to fund the Open Access publishing fees for publications arising from post-grant FP7 projects. This 2-year initiative, called the FP7 Post-Grant Open Access Pilot and being implemented under the OpenAIRE project, has a 4m euro budget to cover Article Processing Charges (APCs) for journal articles (and BPCs for books) stemming from FP7 projects finished no longer than two years ago at the time a manuscript is accepted for publication. This means that over 8,000 FP7 projects are eligible for funding at the moment, and currently running ones will become eligible as they reach their end-date [read more...]
Posted by diamartin| November 26, 2015
Guest post by Pablo de Castro, LIBEROpen Access Project Officer
Feb 3, 2016
Academics across Europe join #Brexit debate https://t.co/bfj7efwNu3 #papers #feedly
Academics across Europe join #Brexit debate https://t.co/bfj7efwNu3 #papers #feedly
— Wladek Grabinski (@wladek60) February 3, 2016
from Twitter https://twitter.com/wladek60
February 03, 2016 at 02:24PM
via IFTTT
Feb 2, 2016
Summery Tarragona https://t.co/oeqHdoZOcl #papers #art #feedly
Summery Tarragona https://t.co/oeqHdoZOcl #papers #art #feedly
— Wladek Grabinski (@wladek60) February 2, 2016
from Twitter https://twitter.com/wladek60
February 02, 2016 at 10:59AM
via IFTTT
Feb 1, 2016
MNF2016 CALL FOR ABSTRACTS
MNF2016
CALL FOR ABSTRACTS
(Extended Deadline to 8 April 2016)
Following numerous requests, we [MNF TPC] have decided to base the proceedings on extended abstracts (of 1-2 pages length) instead of longer proceedings papers. You are not requested to submit a 6-8 pages proceedings paper now.
Those of you who have already submitted your abstracts have the opportunity to extend them to 2 pages to include 1 or 2 figures or tables, if you so wish.
We will keep the abstract submissions open now until the 8 April 2016. Again, submissions need to be pdfs. The extended abstracts should follow the formatting guidelines given in the proceedings paper template given on the webpage.
January’s #FOSS Top Ten https://t.co/O8kFAuzCvR #opensource #feedly
January’s #FOSS Top Ten https://t.co/O8kFAuzCvR #opensource #feedly
— Wladek Grabinski (@wladek60) February 1, 2016
from Twitter https://twitter.com/wladek60
February 01, 2016 at 10:44AM
via IFTTT
#GPIO #Zero and Raspberry #Pi programming starter projects https://t.co/L8pcIPyInw #opensource #feedly
#GPIO #Zero and Raspberry #Pi programming starter projects https://t.co/L8pcIPyInw #opensource #feedly
— Wladek Grabinski (@wladek60) February 1, 2016
from Twitter https://twitter.com/wladek60
February 01, 2016 at 10:43AM
via IFTTT
Jan 31, 2016
Jonathan Riddell: #FOSDEM Photos https://t.co/k7j4SC1P82 #opensource #feedly
Jonathan Riddell: #FOSDEM Photos https://t.co/k7j4SC1P82 #opensource #feedly
— Wladek Grabinski (@wladek60) January 31, 2016
from Twitter https://twitter.com/wladek60
January 31, 2016 at 08:07PM
via IFTTT
Distro or Desktop? You Say Both https://t.co/30hR34EK1I #opensource #feedly #fosdem
Distro or Desktop? You Say Both https://t.co/30hR34EK1I #opensource #feedly #fosdem
— Wladek Grabinski (@wladek60) January 31, 2016
from Twitter https://twitter.com/wladek60
January 31, 2016 at 07:57PM
via IFTTT
Costales: My #Ubuntu Phone is my 'mini' PC for #traveling https://t.co/3iRvIt3DW1 #opensource #feedly
Costales: My #Ubuntu Phone is my 'mini' PC for #traveling https://t.co/3iRvIt3DW1 #opensource #feedly
— Wladek Grabinski (@wladek60) January 31, 2016
from Twitter https://twitter.com/wladek60
January 31, 2016 at 01:57PM
via IFTTT
Jan 29, 2016
postdoctoral positions in Compact Modeling in Tarragona (Spain)
As Professor in the Universitat Rovira i Virgili (Tarragona, Catalonia, Spain), I am going to apply for two postdoctoral positions (funded by the Spanish Ministry and the Catalan Government) related to our research projects about Compact Modeling of semiconductor devices: in particular, the European Union -funded "DOMINO" project (of which I am the coordinator, and which targets modeling of organic and oxide TFTs), and our national projects addressing the modeling of GaN HEMTs and nanowire MOSFETs.
The candidate for one of the position should be a person who holds a PhD as awarded between January 1 2014 and December 31 2015. The candidate for the other position should be a person who holds a PhD as awarded between January 1 2011 and December 31 2013. The duration of both fellowships will be 24 months.
The candidate should have enough research experience in the field of semiconductor devices, and must have a very good knowledge of the physics of electron devices. The research project to be carried out can be adapted to the candidate's profile. In any case, it will be related to the research projects in which we participate. Our contribution in these projects is the physics and modeling (in particular compact modeling) of the novel devices addressed by our projects: organic and oxide Thin Film Transistors (TFTs), GaN HEMTs, nanowire FETs, multi-gate MOSFETs (FinFETs, DG MOSFETs,...), ...
The postdoc positions, which will be a contract, will have a duration of 2-3 years. The net salary will be around 1900 Euro/months.
The candidate for one of the position should be a person who holds a PhD as awarded between January 1 2014 and December 31 2015. The candidate for the other position should be a person who holds a PhD as awarded between January 1 2011 and December 31 2013. The duration of both fellowships will be 24 months.
The candidate should have enough research experience in the field of semiconductor devices, and must have a very good knowledge of the physics of electron devices. The research project to be carried out can be adapted to the candidate's profile. In any case, it will be related to the research projects in which we participate. Our contribution in these projects is the physics and modeling (in particular compact modeling) of the novel devices addressed by our projects: organic and oxide Thin Film Transistors (TFTs), GaN HEMTs, nanowire FETs, multi-gate MOSFETs (FinFETs, DG MOSFETs,...), ...
The postdoc positions, which will be a contract, will have a duration of 2-3 years. The net salary will be around 1900 Euro/months.
The postdoctoral researcher will work in the compact device team, led by Prof Benjamin Iñiguez, belonging to the Nanoelectronics and Photonics Systems Group (NEPHOS) in the Department of Electronic, Electrical and Automatic Control Engineering of the Universitat Rovira i Virgili (URV). This team is a worldwide well recognized pioneering group in the development of compact models for advanced and emerging semiconductor devices. The team has participated in a number of European Union funded projects aout this topic and has led some of them.
Interested applicants should send me their CV by e-mail.
DEADLINE TO RECEIVE APPLICATIONS: February 2 2016
MY E-MAIL ADDRESS IS: benjamin.iniguez@gmail.com
Address:
Benjamin Iñiguez
Nanoelectronics and Photonics Systrems Group (NEPHOS)
Department of Electronic Engineering
Universitat Rovira i Virgili (URV)
Avinguda dels Paisos Catalans 26
43007 Tarragona
SPAIN.
About Tarragona:
Interested applicants should send me their CV by e-mail.
DEADLINE TO RECEIVE APPLICATIONS: February 2 2016
MY E-MAIL ADDRESS IS: benjamin.iniguez@gmail.com
Address:
Benjamin Iñiguez
Nanoelectronics and Photonics Systrems Group (NEPHOS)
Department of Electronic Engineering
Universitat Rovira i Virgili (URV)
Avinguda dels Paisos Catalans 26
43007 Tarragona
SPAIN.
About Tarragona:
Tarragona is located on the Mediterranean, in the heart of the Costa Daurada, in the south of Catalonia, about 100 Km south from Barcelona. Tarragona is well connected to Barcelona by highway, and frequent trains and buses. It has also a direct bus connection with Barcelona Airport. Besides, it has high-speed rail connection with Madrid and Barcelona.
Tarraco (the Roman name for Tarragona) was one of the most important cities in the Roman Empire. F On 30 November 2000, the UNESCO committee officially declared the Roman archaeological complex of Tàrraco a World Heritage Site. This recognition is intended to help ensure the conservation of the monuments, as well as to introduce them to the broader international public. Among the citizens of Tarragona, it has moreover fomented knowledge of, pride in and respect for the city.
Speaking about Tarraco’s climate, the famous Roman poet Virgil wrote: “The climate blends and confuses the seasons singularly, so that all the year seems an eternal spring.” Thanks to its temperate climate, with an average yearly temperature of 23ºC, its clean beaches with fine and gloden sand, and its singular artistic and architectural heritage, Tarragona is one of the most important tourism hubs in Europe. The city has a population of 120,202 inhabitants
8 non-code ways to contribute to open source https://t.co/jiLLIjpEWA #opensource #feedly https://t.co/yWub17oi7E
8 non-code ways to contribute to open source https://t.co/jiLLIjpEWA #opensource #feedly https://t.co/yWub17oi7E
— Wladek Grabinski (@wladek60) January 29, 2016
from Twitter https://twitter.com/wladek60
January 29, 2016 at 03:56PM
via IFTTT
8 non-code ways to contribute to open source https://t.co/jiLLIjpEWA #opensource #feedly
8 non-code ways to contribute to open source https://t.co/jiLLIjpEWA #opensource #feedly
— Wladek Grabinski (@wladek60) January 29, 2016
from Twitter https://twitter.com/wladek60
January 29, 2016 at 03:48PM
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Journal of Luminescence | Vol 170, Part 3, Pgs 749-888, (February 2016) #papers https://t.co/uGxgAEm6NC https://t.co/VWAdjOBV3Z
Journal of Luminescence | Vol 170, Part 3, Pgs 749-888, (February 2016) #papers https://t.co/uGxgAEm6NC https://t.co/VWAdjOBV3Z
— Wladek Grabinski (@wladek60) January 29, 2016
from Twitter https://twitter.com/wladek60
January 29, 2016 at 03:14PM
via IFTTT
Jan 28, 2016
Silicon Photonics - from promise to reality in datacentres https://t.co/LBPxGacO50 #semi #feedly #papers https://t.co/vzf5gF77vD
Silicon Photonics - from promise to reality in datacentres https://t.co/LBPxGacO50 #semi #feedly #papers https://t.co/vzf5gF77vD
— Wladek Grabinski (@wladek60) January 28, 2016
from Twitter https://twitter.com/wladek60
January 28, 2016 at 02:12PM
via IFTTT
Silicon Photonics - from promise to reality in datacentres https://t.co/LBPxGacO50 #semi #feedly #papers
Silicon Photonics - from promise to reality in datacentres https://t.co/LBPxGacO50 #semi #feedly #papers
— Wladek Grabinski (@wladek60) January 28, 2016
from Twitter https://twitter.com/wladek60
January 28, 2016 at 02:06PM
via IFTTT
Special Issue: Planar Fully-Depleted SOI technology https://t.co/gM2tHCE84M #papers
Special Issue: Planar Fully-Depleted SOI technology https://t.co/gM2tHCE84M #papers
— Wladek Grabinski (@wladek60) January 28, 2016
from Twitter https://twitter.com/wladek60
January 28, 2016 at 07:49AM
via IFTTT
Jan 27, 2016
How quality control could save your science https://t.co/FGxeOfhjZB #papers #feedly
How quality control could save your science https://t.co/FGxeOfhjZB #papers #feedly
— Wladek Grabinski (@wladek60) January 27, 2016
from Twitter https://twitter.com/wladek60
January 27, 2016 at 04:59PM
via IFTTT
Linux and #opensource are the future https://t.co/UoiRSK3rqE #opensource #feedly
Linux and #opensource are the future https://t.co/UoiRSK3rqE #opensource #feedly
— Wladek Grabinski (@wladek60) January 27, 2016
from Twitter https://twitter.com/wladek60
January 27, 2016 at 03:33PM
via IFTTT
Building a FOSS Force Community https://t.co/ZPzX3Kh4NK #opensource
Building a FOSS Force Community https://t.co/ZPzX3Kh4NK #opensource
— Wladek Grabinski (@wladek60) January 26, 2016
from Twitter https://twitter.com/wladek60
January 27, 2016 at 12:03AM
via IFTTT
Jan 26, 2016
Nanowire Transistors Could Let You Talk, Text, and Tweet Longer https://t.co/B0KDYiABR7 #papers
Nanowire Transistors Could Let You Talk, Text, and Tweet Longer https://t.co/B0KDYiABR7 #papers
— Wladek Grabinski (@wladek60) January 26, 2016
from Twitter https://twitter.com/wladek60
January 26, 2016 at 11:33PM
via IFTTT
[mos-ak] [2nd Announcement and Call for Papers] Spring MOS-AK Workshop Dresden March 18, 2016
Spring MOS-AK Workshop
Dresden March 18, 2016
2nd Announcement and Call for Papers
Dresden March 18, 2016
2nd Announcement and Call for Papers
Together with the MOS-AK Workshop Scientific Program Coordinators Larry Nagel and Andrei Vladimirescu, local workshop organizers Martin Claus and Sandra Bley as well as Extended MOS-AK TPC Committee, we have pleasure to invite to the MOS-AK Workshop which will be held in Dresden in the DATE Conference timeframe. Planned MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors.
Important Dates:
Call for Papers - Dec. 20152nd Announcement - Jan. 2016Final Workshop Program - Feb. 2016
MOS-AK Workshop: March 18, 2016
09:00 - 10:30 - Morning MOS-AK Session11:00 - 12:00 - CM Standardization Panel12:00 - 13:00 - Lunch13:00 - 16:00 - Afternoon MOS-AK Session
Venue:
Center for Advancing Electronics Dresden (CFAED)Technische Universität DresdenWürzburger Str. 4601187 DresdenGermany
Topics to be covered include the following:
- Advances in semiconductor technologies and processing
- Compact Modeling (CM) of the electron devices
- Verilog-A language for CM standardization
- New CM techniques and extraction software
- Open Source TCAD/EDA modeling and simulation
- CM of passive, active, sensors and actuators
- Emerging Devices, CMOS and SOI-based memory cells
- Microwave, RF device modeling, high voltage device modeling
- Nanoscale CMOS devices and circuits
- Technology R&D, DFY, DFT and reliability/ageing IC Designs
- Foundry/Fabless Interface Strategies
Online MOS-AK Abstract Submission:
Authors should submit an abstract using on-line MOS-AK submission form:
Authors should submit an abstract using on-line MOS-AK submission form:
http://www.mos-ak.org/dresden_2016/abstracts.php
(any related inquiries can be sent to abstracts@mos-ak.org)
Free Online Workshop Registration:
Free Online Workshop Registration:
http://www.mos-ak.org/dresden_2016/registration.php
(any related inquiries can be sent to register@mos-ak.org)
Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of High Speed Electronics and Systems
Extended MOS-AK Committee
(any related inquiries can be sent to register@mos-ak.org)
Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of High Speed Electronics and Systems
Extended MOS-AK Committee
(WG 26012016)
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ArduinoPhone 2.0 - An #opensource mobile phone https://t.co/17knLM0cC1 #todo #feedly
ArduinoPhone 2.0 - An #opensource mobile phone https://t.co/17knLM0cC1 #todo #feedly
— Wladek Grabinski (@wladek60) January 26, 2016
from Twitter https://twitter.com/wladek60
January 26, 2016 at 10:56AM
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Visit Brussels and learn about open source at #FOSDEM 2016 https://t.co/HzplsOxRbm #opensource #feedly
Visit Brussels and learn about open source at #FOSDEM 2016 https://t.co/HzplsOxRbm #opensource #feedly
— Wladek Grabinski (@wladek60) January 26, 2016
from Twitter https://twitter.com/wladek60
January 26, 2016 at 10:45AM
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Unified Compact #Model Covering Drift-Diffusion to Ballistic Carrier Transport https://t.co/sr4HBeYi4g #papers #feedly
Unified Compact #Model Covering Drift-Diffusion to Ballistic Carrier Transport https://t.co/sr4HBeYi4g #papers #feedly
— Wladek Grabinski (@wladek60) January 26, 2016
from Twitter https://twitter.com/wladek60
January 26, 2016 at 08:09AM
via IFTTT
Jan 25, 2016
ISSCC Focuses on Image Processors for Autonomous Cars #modeling https://t.co/U587enncd1
ISSCC Focuses on Image Processors for Autonomous Cars #modeling https://t.co/U587enncd1
— Wladek Grabinski (@wladek60) January 25, 2016
from Twitter https://twitter.com/wladek60
January 25, 2016 at 08:43PM
via IFTTT
Jan 22, 2016
Compact #Model Parameter Extraction Using Bayesian Inference, Incomplete New Measurements, and Optima... https://t.co/5C3aRdoBqA
Compact #Model Parameter Extraction Using Bayesian Inference, Incomplete New Measurements, and Optima... https://t.co/5C3aRdoBqA
— Wladek Grabinski (@wladek60) January 22, 2016
from Twitter https://twitter.com/wladek60
January 22, 2016 at 11:18PM
via IFTTT
Leakage current minimisation and power reduction techniques using sub-threshold design #modeling https://t.co/71Ah4ALDEB
Leakage current minimisation and power reduction techniques using sub-threshold design #modeling https://t.co/71Ah4ALDEB
— Wladek Grabinski (@wladek60) January 22, 2016
from Twitter https://twitter.com/wladek60
January 22, 2016 at 05:17PM
via IFTTT
Analytical #Model for the Dynamic Behavior of Triple-Gate Junctionless Nanowire Transistors https://t.co/ox0DFIspyF
Analytical #Model for the Dynamic Behavior of Triple-Gate Junctionless Nanowire Transistors https://t.co/ox0DFIspyF
— Wladek Grabinski (@wladek60) January 22, 2016
from Twitter https://twitter.com/wladek60
January 22, 2016 at 02:59PM
via IFTTT
Compact #Modeling of Magnetic Tunneling Junctions https://t.co/sl9NaOEg4G
Compact #Modeling of Magnetic Tunneling Junctions https://t.co/sl9NaOEg4G
— Wladek Grabinski (@wladek60) January 22, 2016
from Twitter https://twitter.com/wladek60
January 22, 2016 at 02:52PM
via IFTTT
Parasitic Capacitance Analytical #Modeling for Sub-7-nm Multigate Devices https://t.co/z8Q8IcuINM
Parasitic Capacitance Analytical #Modeling for Sub-7-nm Multigate Devices https://t.co/z8Q8IcuINM
— Wladek Grabinski (@wladek60) January 22, 2016
from Twitter https://twitter.com/wladek60
January 22, 2016 at 02:47PM
via IFTTT
Parasitic Capacitance Analytical Model for Sub-7-nm Multigate Devices #modeling https://t.co/9Q50HGFkni
Parasitic Capacitance Analytical Model for Sub-7-nm Multigate Devices #modeling https://t.co/9Q50HGFkni
— Wladek Grabinski (@wladek60) January 22, 2016
from Twitter https://twitter.com/wladek60
January 22, 2016 at 02:44PM
via IFTTT
Jan 19, 2016
FOSDEM 2016 EDA Devroom
FOSDEM 2016: EDA Devroom
Room: AW1.121
Saturday, 30 January 2016
Software developers have a much easier time sharing their developments than hardware designers. When you put a piece of code on the Web, you don't ask yourself if others will have the freedom and resources to access a text editor to look at it and modify it, or a compiler or interpreter to have the code do something useful. The landscape for hardware designs is more complicated. The dominant design and simulation tools are proprietary, and there is not even a de-facto proprietary standard format to share designs. The Electronic Design Automation (EDA) Devroom looks at recent progress in Free CAD/EDA Tools for hardware design and simulation, and serves as a meeting place for discussion about future collaborations and FOSS developments. Come and see how some of these tools are actually catching up, and sometimes even more, in terms of features and quality.
[EDA Devroom Detailed Agenda]
Jan 18, 2016
NEEDS Berkeley Workshop 2016
Modelling using Verilog-A in MAPP: A Hands-On Workshop
8 AM - 6 PM
Thursday, Feb 4, 2016
University of California, Berkeley
Berkeley, CA 94720
Berkeley's Model and Algorithm Prototyping Platform (MAPP) is a MATLAB-based platform that provides a complete environment for developing, testing, experimentally validating, and inserting compact models in open source simulation platforms. It is also useful for prototyping new simulation algorithms.
This hands-on workshop will focus on the newly developed Verilog-A to ModSpec device model translator for MAPP, dubbed VAPP (Verilog-A Parser and Processor). The goal of the workshop is to illustrate how VAPP/MAPP facilitates the development of simulation ready compact models. An overview of MAPP's multi-physics modelling and simulation capabilities will also be provided. A hands-on refresher on MAPP will be provided for those who have no prior experience with it.
Please bring your laptop (running linux, OSX or Windows). It would be very helpful if you already have MATLAB installed and running on your laptop; otherwise you may need to access the hands-on components through the web.
For more information about MAPP, see: https://nanohub.org/groups/needs/mapp
Travel support will be available for NEEDS students. Please try to share a room, and ask your advisor to e-mail Mark Lundstrom at lundstro@purdue.edu for travel support.
For other questions, please contact Vicki Johnson at vicki@purdue.edu
Dec 16, 2015
[video] How to Model RF Passive Components: Capacitors and Resistors
This video explains and demonstrates a method to develop accurate SPICE models from verified S-parameter measurements. By using an easy to follow, step by step procedure, this video walks you through the entire modeling flow for an on-wafer capacitor, using the Keysight Measurement and Modeling Software IC-CAP.
The IC-CAP project can be downloaded, together with a detailed How-to-Use description, and an in-depth tutorial about passive components modeling, applying the demonstrated method.
[VIDEO]
The IC-CAP project can be downloaded, together with a detailed How-to-Use description, and an in-depth tutorial about passive components modeling, applying the demonstrated method.
[VIDEO]
Nov 18, 2015
[mos-ak] [Final Program] 8th International MOS-AK Workshop Washington DC December 9, 2015
8th International MOS-AK Workshop
Washington DC December 9, 2015
The Final MOS-AK Workshop Program
Washington DC December 9, 2015
The Final MOS-AK Workshop Program
Together with the MOS-AK Workshop Scientific Program Coordinators Larry Nagel and Andrei Vladimirescu, as well as Extended MOS-AK TPC Committee, we have pleasure to invite to the MOS-AK Workshop which will be held in Washington DC in the IEDM / CMC meetings timeframe on December 9, 2015. The MOS-AK workshop is organized with aims to strengthen an academic/industry network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors.
Venue:
Embassy of Switzerland
2900 Cathedral Ave, NW,
Washington, DC 20008
USA
2900 Cathedral Ave, NW,
Washington, DC 20008
USA
Free Online Workshop Registration:
http://www.mos-ak.org/washington_dc_2015/registration.php
(any related inquiries can be sent to register@mos-ak.org)
(any related inquiries can be sent to register@mos-ak.org)
Workshop Agenda:
- MOS-AK Workshop - Dec, 9, 2015
- Online Technical Program http://www.mos-ak.org/
washington_dc_2015/ - 08:30 - 09:00 - On-site Registration
- 09:00 - 12:30 - Morning MOS-AK Session
- TCAD and Advanced CMOS Technologies
- Compact Modeling and Reliability Co-simulation
- 12:30 - 13:30 - Lunch
- 13:30 - 17:00 - Afternoon MOS-AK Session
- CMC Compact Model Standardization
- FOSS Tools for Compact Model Verilog-A Standardization
- 17:00 End of the workshop
Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication in a special compact modeling issue of the International Journal of High Speed Electronics and Systems (IJHSES)
Extended MOS-AK Committee
Selected best MOS-AK technical presentation will be recommended for further publication in a special compact modeling issue of the International Journal of High Speed Electronics and Systems (IJHSES)
Extended MOS-AK Committee
WG/18/11/15
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Nov 11, 2015
[ESSCIRC 2015] Low-power analog RF circuit design based on the inversion coefficient
[ref] Enz, Christian; Chalkiadaki, Maria-Anna; Mangla, Anurag, "Low-power analog/RF circuit design based on the inversion coefficient," in ESSCIRC 2015 - 41st , vol., no., pp.202-208, 14-18 Sept. 2015
Keywords: Analytical models, Integrated circuits, Noise, Radio frequency, Silicon, Transconductance, Transistors, BSIM6
URL / doi: 10.1109/ESSCIRC.2015.7313863
Abstract: This paper discusses the concept of the inversion coefficient as an essential design parameter that spans the entire range of operating points from weak via moderate to strong inversion, including velocity saturation. Several figures-of-merit based on the inversion coefficient, especially suitable for the design of low-power analog and RF circuits, are presented. These figures-of-merit incorporate the various trade-offs encountered in analog and RF circuit design. The use of the inversion coefficient and the derived figures-of-merit for optimization and design is demonstrated through simple examples. Finally, the simplicity of the inversion coefficient based analytical models is emphasized by their favorable comparison against measurements of a commercial 40-nm bulk CMOS process as well as with simulations using the BSIM6 model.
Keywords: Analytical models, Integrated circuits, Noise, Radio frequency, Silicon, Transconductance, Transistors, BSIM6
URL / doi: 10.1109/ESSCIRC.2015.7313863
Oct 29, 2015
[Call for Participation] FOSDEM 2016 Electronic Design Automation Devroom
Call for Participation
FOSDEM 2016 Electronic Design Automation Devroom
This is the call for participation in the FOSDEM 2016 devroom on Free/Open Source Software (FOSS) Electronic Design Automation (EDA) tools, to be held on Saturday 30 January 2016 in Brussels, Belgium. We are looking for contributions under the form of talks covering the following main topics:
- Printed Circuit Board (PCB) design tools (e.g. KiCad and gEDA)
- Analogue and digital simulators (e.g. ngspice, Qucs, Gnucap, Xyce, GHDL, Icarus and Verilator)
- Any other EDA tools such as high-level tools for digital hardware design (e.g. Migen)
- Inter-project opportunities for collaboration
We hope to provide an opportunity for attendees to bring themselves up to date on the latest FOSS EDA developments, share knowledge and identify opportunities to collaborate on development tasks. Have a look at last year's event for a taste of what the EDA devroom is about.
The submission process
Please submit your proposals at https://penta.fosdem.org/submission/FOSDEM16
Please submit your proposals at https://penta.fosdem.org/submission/FOSDEM16
before 4 December 2015.
If you already have a Pentabarf account (for example as a result of having submitted a proposal in the past), make sure you use it to log in and submit your proposal. Do not create a new account if you already have one. Please provide a bit of information about yourself under Person -> Description -> Abstract. When you submit your proposal (creating an "Event" in Pentabarf), make sure you choose the "EDA devroom" in the track drop-down menu. Otherwise your proposal might go unnoticed. Fill in at least a title and abstract for the proposed talk and a suggested duration. Bear in mind that a lot of the value in these meetings comes from the discussions, so please be reasonable regarding the duration of the talk.
Important dates
- 4 December 2015: deadline for submission of proposals
- 18 December 2015: announcement of final schedule
- 30 January 2016: devroom day
Oct 23, 2015
[Purdue e-Pubs] A physics-based compact model for thermoelectric devices
A physics-based compact model for thermoelectric devices
Kyle Conrad, Purdue University; Mark S. Lundstrom, Purdue University (Advisor)
Abstract: Thermoelectric devices have a wide variety of potential applications including as coolers, temperature regulators, power generators, and energy harvesters. During the past decade or so, new thermoelectric materials have been an active area of research. As a result, several new high figure of merit (zT) materials have been identified, but practical devices using these new materials have not yet been reported. A physics-based compact model could be used to simulate a thermoelectric devices within a full system using SPICE-compatible circuit simulators. If such a model accepts measured or simulated material parameters, it would be useful in exploring the system level applications of new materials. In this thesis, the ground work for such a compact model is developed and tested. I begin with a discussion of thermoelectric transport theory within the Landauer formalism. The Landauer formalism is used as the basis of the tool LanTraP, which uses full band descriptions to calculate the distribution of modes and thermoelectric transport parameters, which can serve as the input to a compact model. Next, an equivalent circuit model is presented, explained, and tested using a simple Bi2Te 3 thermoelectric leg. The equivalent circuit is shown to perform well under a variety of DC, transient, and AC small signal operating conditions. With the equivalent circuit it is easy to determine the maximum cold side temperature drop, the maximum cold side heat absorbed, the temperature profile within the leg, the temperature response to a pulsed current, and impedance over a range of frequencies. Finally, Sentaurus®, a computer program that solves the thermoelectric transport equations numerically, is used to compare and benchmark some of the results of the equivalent circuit when considering Si as the thermoelectric material. The equivalent circuit and Sentaurus® simulations produce similar results in DC and transient cases, but in the AC small signal case the two simulations produce slight differences. The results of this work establishes a baseline compact model for thermoelectric devices whose accuracy and capabilities can be extended.
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