Sunday, 7 February 2016

Device to GDSII for IC Design Training

Hands on Training Program on “Device to GDSII for IC Design”
on 22-27 Feb 2016
Organized by VLSI Division of School of Electronics Engineering
Vellore Institute of Technology, Near Katpadi Rd Vellore, Tamil Nadu - 632014


The relentless march fast of the CMOS has slowed down and the semiconductor industry is looking for novel and innovative devices. Many novel devices are being explored currently. TCAD and Cadence tool allows us to generate new structures, circuits and analyze its performance. Unlike other circuit simulators, TCAD and Cadence needs a special training. This hands on training addresses this gap.

Target Audience: Faculty, students and research scholars from various engineering colleges of India. The number of participants is limited to 40. 

Topics to ďe addressed:

Using TCAD:
  • Structure Creation, Simulation and Device Simulation 
  • Process Simulation 
  • Multi-gate Transistors 
  • Radiation study on devices and circuits
Using Cadence: 
  • RTL Design and Simulation 
  • Synthesis and low power synthesis Using RTL Compiler 
  • Physical aware synthesis and DFT 
  • Block and Top Level P&R Using SOC Encounter 
  • STA Using Timing Engine 


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