[Call for Papers] SISPAD2014

https://sites.google.com/site/sispad2014/

This is a call for papers for the 2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD2014), to be held September 9-11, 2014, in Yokohama, Japan. This conference provides an opportunity for the presentation and discussion of the latest advances in modeling and simulation of semiconductor devices, processes, and equipment for integrated circuits.

Abstract submission deadline is March 31, 2014.

Workshops:
Two companion workshops will run concurrently prior to the start of the conference on Monday 8th September 2014:

• Workshop 1: Compact Modeling -Enabling Better Insight of Device Features-
  Organizer: Mitiko Miura-Mattausch (Hiroshima University)
• Workshop 2: Carrier Transport in Nano-MOS Transistors: Theory and Experiments(tentative)
  Organizer: Hideaki Tsuchiya (Kobe University) and Yoshinari Kamakura (Osaka University)

Plenary Speakers:

• Augusto Benvenuti (Micron Technology)
  Current status and future prospects of non-volatile memory modeling
• Massimo V. Fischetti (University of Texas at Dallas)
  Physics of electronic transport in low-dimensionality materials forfuture FETs
• Kimimori Hamada (Toyota Motor Corporation)
  TCAD challenge on development of power semiconductor devices for automotive applications

Invited Speakers:

• Mario Ancona (Naval Research Laboratory)
  Nonlinear thermoelectroelastic simulation of III-N devices
• Asen Asenov (University of Glasgow)
  Progress in the simulation of time dependent statistical variability in nano CMOS transistors
• Jean-Pierre Colinge (Taiwan Semiconductor Manufacturing Company)
  Nanowire transistors: pushing Moore's law to the limit
• Tibor Grasser (Vienna University of Technology)
  Advanced modeling of charge trapping: RTN, 1/f noise, SILC, and BTI
• Kohji Mitsubayashi (Tokyo Medical and Dental University)
  Novel biosensing devices for medical applications
• Christian Sandow (Infineon Technologies)
  Exploring the limits of the safe operation area of power semiconductor devices
• Mark Stettler (Intel Corporation)
  Device and process modeling: 20 years at Intel's other fab

Call for IJNM papers: Noise modeling of high-frequency semiconductor devices

INTERNATIONAL JOURNAL OF NUMERICAL MODELLING: ELECTRONIC NETWORKS, DEVICES AND FIELDS Int. J. Numer. Model. (2014)

Call for IJNM papers: Noise modeling of high-frequency semiconductor devices 

Noise processes in solid-state active devices often determine their fundamental operational limits. This is especially true in situations where a device operates under tight sensitivity and accuracy constraints, as is the case in satellite communication systems, aerospace instrumentation, and deep-space radio astronomy. Today’s ultra-high frequency transistors that meet these demanding low-noise performance characteristics often leverage progressive device downscaling techniques in conjunction with improved semiconductor alloys. 

To enable the design of next-generation low-noise devices, however, accurate and flexible models that characterize the connection between the physics of microscopic noise processes and measurable macroscopic performance are called for. The objective of this Special Issue is to collect and disseminate recent results addressing the topic of modeling and simulation of the macroscopic noise performance of high- frequency transistors including but not limited to GaAs-based and GaN-based field-effect transistors, Si metal–oxide–semiconductor FETs and FinFETs, InP-based high-electron-mobility transistors, and GaAs and SiGe heterojunction bipolar transistors. It is worth pointing out that because of frequency up-conversion phenomena caused by a device’s nonlinearities, low frequency noise processes may strongly impact microwave and millimeter wave behavior as well. Contributions focusing on low-frequency noise modeling therefore will be considered as well. 

This issue will include both invited and contributed manuscripts.

Manuscripts for this Special Issue should adhere to the requirements for regular papers of the IJNM as specified in the Author Guidelines at 

http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1099-1204/ homepage/ForAuthors.html. 

Potential contributors may contact the Guest Editors to determine the suitability of their contribution to the Special Issue. All manuscripts should be submitted via the IJNM’s manuscript website, with a statement that they are intended for this Special Issue. 

Guest Editors: 
Prof. Alina Caddemi University of Messina, Italy Email:
Prof. Ernesto Limiti University of Rome Tor Vergata, Italy Email:

Manuscript submission deadline: July 31, 2014

Compact DC Modeling of Organic Field-Effect Transistors: Review and Perspectives

In spite of impressive improvements achieved for organic field-effect transistors (OFETs), there is still a lack of theoretical understanding of their behaviors. Furthermore, it is challenging to develop a universal model that would cover a huge variety of materials and device structures available for state-of-the-art OFETs. Nonetheless, currently there is a strong need for specific OFET compact models when device-to-system integration is an important issue. We briefly describe the most fundamental characters of organic semiconductors and OFETs, which set the bottom line dictating the requirement of an original model different from that of conventional inorganic devices. Along with an introduction to the principles of compact modeling for circuit simulation, a comparative analysis of the reported models is presented with an emphasis on their primary assumptions and applicability aspects. Critical points for advancing OFET compact models are discussed in consideration of the recent understanding of device physics.

[1] Kim, C.-H.; Bonnassieux, Y.; Horowitz, G., "Compact DC Modeling of Organic Field-Effect Transistors: Review and Perspectives," Electron Devices, IEEE Transactions on , vol.61, no.2, pp.278,287, Feb. 2014
doi: 10.1109/TED.2013.2281054
URL

[Final Program] EUROSOI 2014, Tarragona, Catalonia, Spain; January 27-29, 2014

The 10th Workshop of the Thematic Network
on Silicon on Insulator Technology, Devices and Circuits 

(EUROSOI 2014) 

Tarragona, Catalonia, Spain 

January 27-29, 2014 

The EUROSOI Workshop is an international forum to promote interaction and exchangesbetween research groups and industrial partners involved in SOI activities all over the world. Following the lively experience of the previous meetings in Granada (2005), Grenoble (2006), Leuven (2007), Cork (2008), Gšteborg (2009), Grenoble (2010), Granada (2011), Montpellier (2012), Paris (2013), EUROSOI 2014 will be held in Tarragona, Catalonia, Spain, and will include a short course program, oral and poster sessions, outstanding key-note presentations, as well as ample rooms for informal discussions. EUROSOI covers recent progress in SOI technologies and will be of interest to materials and device scientists, as well as to process, circuits and applications oriented engineers.

Monday, January 27, 2014

8:30 REGISTRATION
9:05-9:20 SHORT COURSE OPENING
9:20-11:00 PART 1 - EDS MINI-COLLOQUIUM ON SOI TECHNOLOGY 
9:20-10:10 "Process Challenges for Advanced Ge CMOS Technologies" Cor Claeys (IMEC, Leuven, Belgium)
10:10-11.00 "From Floating-Body Memory to Unified Memory on SOI" Sorin Cristoloveanu (INPG, Grenoble, France)
11:00-11:30 COFFEE BREAK
11:30-12:20 "Fabrication Challenges for sub-10 nm Technology nodes" Michael Ostling (KTH, Stockholm, Sweden)
12:20-13:00 "ESD protection of FD and MuG SOI CMOS Chips" Dimitris Ioannou (George Mason University, Fairfax, VA, USA)
13:00-14:30 LUNCH
14:30-15:50 Part 2 -EUROSOI TUTORIAL 
14:30-15:20 "Advanced SOI MOSFET architectures" Jason Woo (UCLA, CA, USA)
15:20-16:00 "SOI CMOS sensors, transistors and circuits for ultra-low-power and harsh environment applications" Denis Flandre (UCL, Louvain-la-Neuve, Belgium)
16:00-16:30 COFFEE BREAK
16:30-18:00 SOI MOSFET CHARACTERIZATION 
16:30-17:20 "On the threshold voltage and interface coupling in advanced SOI MOSFETs" Tamara Rudenko (ISP, Kyiv, Ukraine)
17:20-18:00 "From SOI MOSFET to Spin MOSFET: a modeling approach" Viktor Sverdlov (Tu-Wien, Austria)
20:30 EUROSOI RECEPTION

Tuesday January 28, 2014 

8:15 REGISTRATION
8:45-9:00 OPENING
9:00-11:00 PLENARY SESSIONS 
9:00-9:40 "Taking the next step on advanced HKMG SOI technologies -from 32 nm PD SOIvolume production to 20/28 FD SOI and beyond" Manfred Horstmann (Globalfoundries, Dresden, Germany) invited talk
9:40-10:20 INVITED TALK 
Heike Riel (IBM Research, Zurich) -invited talk
10:20-11:00 "Beyond Si CMOS: Benefits and Challenges " Rafael Rios (Intel, Portland OR, USA) -invited talk
11:00-11:20 COFFEE BREAK
11:20-13:00 SOI MATERIALS TECHNOLOGY AND CHARACTERIZATION 
11:20-11:40 Process and performance of Copper TSVs Lado Filipovic et al.
11:40-12:00 Increasing mobility and spin lifetime with shear strain in thin silicon films Dmitri Osintsev et al.
12:00-12:20 A Comparative Study of Variability of RTN Power Spectral Densities in Bulk and SOIMOSFETs  Louis Gerrer et al.
12:20-12:40 Low temperature noise spectroscopy of p-channel SOI FinFETs Bogdan Cretu et al.
12:40-13:00 Channel Length Influence on the Low-Frequency Noise of Strained 45o Rotated Triple Gate SOI nFinFETs Marcio Alves Sodre de Souza et al.
13:20-14:10 LUNCH
14:10-15:50 SOI MOSFET TECHNOLOGY 
14:10-14:30 Impact of S/D doping profile into electrical properties in nanoscaled UTB2SOI  devices Carlos Sampdero et al.
14:30-14:50 TCAD investigation on a formal Neuron device in 28nm UTBB FDSOI technology Philippe Galy et al.
14:50-15-10 Dual ground plane for high-voltage MOSFET in UTBB FDSOI Technology Antoine Litty et al.
15:10-15:30 Trigate NanoWire MOSFETs Analog Figures of Merit Kilchytska, Valeriya et al.
15:30-15:50 Electrostatically-doped SL FET optimized to meet all the ITRS power targetsat V_DD=0.4 V Elena Gnani et al.
15:50-16:00 COFFEE BREAK
16:00-17:20 SOI MOSFET CHARACTERIZATION 
16:00-16:20 Enhanced Dynamic Threshold Voltage UTBB SOI nMOSFETs Katia Sasaki et al.
16:20-16:40 Parasitic bipolar effect in advanced FD SOI MOSFETs: experimental evidence andgain extraction Fanyu Liu et al.
16:40-17:00 Impact of Lateral Fin-Width Non-Uniformity of FinFETs Clarissa Prawoto et al.
17:00-17:20 Surface effects on split C-V measurements on SOI wafers Luca Pirro et al.
17:20-17:40 Impact of Self-Heating on UTB MOSFET ParametersS ergej Makovejev at al.
17:40-18:00 POSTER BRIEFING (3 MIN EACH) 
18:00-19:40 POSTER SESSION 
Subthreshold Behavior of the PD SOI NMOS Device Considering BJT and DIBL Effects James Kuo et al.
Investigation of Statistical Effects on Reliability of SOI FinFETs Including Sidewall Crystal Orientation Salvatore Amoroso et al.
Powering the More than Moore Electronics with i-MOSLining Zhang et al.
Analysis of Short-Channel Effect in SOTB-MOSFET for Ultra-Low Power Applications Hidenori Miyamoto et al.
2D Analytical Modeling of the Trap-Assisted-Tunneling Current in Double-GateTunnel-FETs Michael Graef et al.
Improved Compact Current Model for FinFETs Based in a New Geometric Approach Arianne Pereira et al.
Capability of the IDS Analytical Model on Predicting the Diamond Variability by Usingthe F-Test Statistic Evaluation Salvador Gimenez et al.
An appraise of the sources of electrical parameters variation in DGMOS Rodrigo Picos et al.
An analytical model for the inversion charge distribution in GAA MOSFETs with rounded corners Francisco Ruiz et al.
The Negative World-line Holding Bias Effect on the Retention Time in FBRAMs Sara Santos et al.
20:30 GALA DINNER

Wednesday January 29, 2014 

8:30-10:30 SOI MOSFET MODELLING 
8:30-8:50 Comprehensive Low-Field Mobility Modeling in Nano-Scaled SOI Channels Zlatan Stanojevic et al.
8:50-9:10 A comprehensive DC current model to describe FinFET self-heating effects Benito Gonz‡lez et al.
9:10-9:30 Channel-Length Impact on Supercoupling Effect in FD-MOSFETs Carlos Navarro et al.
9:30-9:50 Substrate Effect on Threshold Voltage of long and short channel UTBB SOI nMOSFETs Joao Martino et al.
9:50-10:10 In depth characterization of electron transport in 14nm FD-SOI nMOS devices Minju Shin et al.
10:10-10:30 Role of the gate in ballistic nanowire SOI MOSFET Anurag Mangla et al.
10:30-10:50 COFFEE BREAK
10:50-13:10 CIRCUITS, MEMORIES AND SENSORS 
10:50-11:30 "Future of Multi-gate CMOS Technology" Hiroshi Iwai (University of Tokyo, Japan)
11:30-11:50 Impact of SEU on Bulk and FDSOI CMOS SRAM Walter Enrique Calienes Bartra et al.
11:50-12:10 Mechanical Characterization and Modelling of Lorentz Force Based MEMS Magnetic Field Sensors Petros Gkotsis et al.
12:10-12:30 Performance of Source-Follower Buffers Implemented with Junctionless Nanowire nMOS Transistors Michelly Souza et al.
12:30-12.50 PMOSFET-based Pressure Sensors in FD SOI Technology Benoit Olbrechts et al.
12:50-13:10 Performance of Common-Source current mirrors with asymmetric self-cascode SOInMOSFETs  Rafael Assalti et al.
13:10-14:20 LUNCH
14:20-16:10 BEYOND CMOS: NANOWIRES AND JUNCTIONLESS TRANSISTORS 
14:20-15:00 "2D semiconductor channels for ultimate thickness scaling and other versatile applications" Athanasios Dimoulas (IMS, Demokritos, Athens, Greece)
15:00-15:20 A way to solve Poisson equation en cylindrical coordinates to obtain a compact model for Junctionless Gate All Around MOSFET Franois Lime et al.
15:20-15:40 Explicit analytical charge and capacitance models for Junctionless Surrounding GateTransistors  Oana Moldovan et al.
15:40-16:00 Performance Evaluation of Stacked Gate-All-Around MOSFETs Meng-Hsueh Chiang et al.
16:00-16:20 Modeling of Quantization Effects in Nanoscale DG Junctionless MOSFETs Thomas Holtij et al.
16:20-16:30 COFFEE BREAK
16:30-16:50 BEYOND CMOS (TFETs) 
16:30-16:50 Heterojunction TFET inverters providing better performance than multi-gate CMOS at sub 0.3V Vdd Elena Gnani et al.
16:50-17:10 Transport mechanism influence on Vertical Nanowire-TFET analog performance as a function of temperature Paula Agopian et al.
17:10-17:30 3D Modeling of Direct Band-to-Band Tunneling in Nanowire TFETs. Lidija Filipovic et al.
17:30-17:50 Influence of the gate oxide thickness on the Analog Performance of vertical Nanowire-Tunnel FETs with Ge Source Felipe Neves et al.
17:50-18:10 Influence of a precisely positioned channel dopant on the performance of gate-allaround Si nanowire transistor: a full 3D NEGF simulation study Vihar Georgiev et al.
18:10-18:20 CONCLUSIONS AND ANNOUNCEMENTS 

[Final Program] 11th International Workshop on Compact Modeling

11th International Workshop on Compact Modeling (IWCM 14)

January 23 (Thursday), 2014

Suntec Singapore Convention and Exhibition Centre (Room 309)

Workshop Program

9:00-9:10am Welcome address
Mansun Chan (workshop chair)

Session I: Modeling for Compact Semiconductor
Session Chair: Lining Zhang

9:10-9:35am Challenges and Prospects of Compact Modeling for Future Generation III-V/Si Co-integrated ULSI Circuit Design
Xing Zhou, Siau Ben Chiah, Binit Syamal, Hongtao Zhou, Arjun Ajaykumar, and Xu Liu; Nanyang Technological University, Singapore
9:35-10:00am A Large Signal Model for InP/InGaAs Double Heterojunction Bipolar Transistors
Yan Wang and Yuxia Shi; Tsinghua University, China
10:00-10:25am Analytical Modeling for AlGaN/GaN HEMTs
Aixi Zhang, Lining Zhang, Zhikai Tang, Xiaoxu Cheng*, Yan Wang*, Kevin J. Chen, and Mansun Chan; The Hong Kong University of Science and Technology, Hong Kong, China; *Tsinghua University, China

10:25-10:40am Break

Session II: Non-Classical Device Modeling and Platform
Session Chair: Xing Zhou

10:40-11:05am Developing i-MOS as a Compact Model Standardization Platform
Lining Zhang and Mansun Chan; The Hong Kong University of Science and Technology, Hong Kong, China
11:05-11:30am An Analytic Model for Nanowire Tunnel-FETs
Ying Liu, Jin He, Mansun Chan*, Caixia Du**, Yun Ye, Wei Zhao, Wen Wu and Wenping Wang; Peking University Shenzhen SOC Key Laboratory, China; *The Hong Kong University of Science and Technology, Hong Kong, China; **Shenzhen Huayue Teracale Chip Electronic Limited Co., China
11:30-11:55am A Channel Potential Based Model for SiO2- Core Si-Shell SRGMOSFET
Xiangyu Zhang, Jin He, Mansun Chan*, Caixia Du**, Yun Ye, Wei Zhao, Wen Wu and Wenping Wang; Peking University Shenzhen SOC Key Laboratory, China; *The Hong Kong University of Science and Technology, Hong Kong, China; **Shenzhen Huayue Teracale Chip Electronic Limited Co., China

11:55am-2:00pm Lunch

Session III: Power Device Modeling
Session Chair: Young June Park

2:00-2:25pm Compact Modeling of the Reverse Recovery Effect in LDMOS Body Diode (Invited)
M. Miyake; Hiroshima University, Japan
2:25-2:50pm Compact Modeling of the SiC IGBT Including the Switching at High Temperature
K. Matsuura, M. Miura-Mattausch, M. Miyake and H. J. Mattausch; Hiroshima University, Japan
2:50-3:15pm Experimental Verification of Power MOSFET Model under Switching Operations
A. Saito, M. Miura-Mattausch, M. Miyake, T. Umeda and H.J. Mattausch; Hiroshima University, Japan

3:15-3:30pm Break

Session IV: Reliability Modeling
Session Chair: Jin He

3:30-3:55pm 3D Monte Carlo Reaction-Diffusion Simulation Framework to model Time Dependent Dielectric Breakdown in BEOL Oxide
Seong Wook Choi and Young June Park; Seoul National University, Korea
3:55-4:20pm Development of NBTI and Channel Hot Carrier (CHC) Effect Models and their Application for Circuit Aging Simulation
Chenyue Ma, Hans Jürgen Mattausch, Kazuya Matsuzawa*, Seiichiro Yamaguchi*, Teruhiko Hoshida*, Masahiro Imade*, Risho Koh*, Takahiko Arakawa* and Mitiko Miura-Mattausch; Hiroshima University, Japan; * Semiconductor Technology Academic Research Center, Japan
4:20-4:45pm Modeling of the Surface Charges on Au Electrode Including Pseudocapacitance
Jooseong Kwon, Intae Jeong, Sungwook Choi and Young June Park; Seoul
National University, Korea

4:45-4:55pm Closing Remarks
Hans Juergen Mattausch (workshop co-chair)

Thanks to  Adele HARS, we can share this post:

The FD-SOI Papers at IEDM ’13

Posted by Adele HARS on December 16, 2013
Tagged with 10nm, 14nm, 28nm, conference, design, FD-SOI, GlobalFoundries, Hitachi, IBM, Leti, manufacturing, R&D, Renesas, silicon-on-insulator, Soitec, ST, strain, Synopsys, U.Tokyo, UTBB FD-SOI was a hot topic at this year’s IEEE International Electron Devices Meeting (IEDM) (www.ieee-iedm.org), the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology.
The FD-SOI papers featured high performance, low leakage, ultra-low power (0.4V),  excellent variability, reliability and scalability down to the 10 nm node using thin SOI and thin BOX substrate. Performance boosters using high mobility materials such as thin strain Si, Ge, and III-V on-Insulator were also presented.
Brief summaries of the FD-SOI papers, culled from the Advance Program (and some of the actual papers) follow.
9.2 High Performance UTBB FDSOI Devices Featuring 20nm Gate Length for 14nm Node and Beyond (STMicroelectronics, Leti, IBM, Renesas, Soitec, GlobalFoundries)

This was the big paper reporting on ST’s flavor of high-performance FD-SOI (UTBB, which stands for ultra-thin-body-and-box) with 20nm gatelength, which target the 14nm node. In addition to excellent results, the paper demonstrated that  “…FD-SOI reliability is superior to Bulk devices.”

[8] C. Auth, et al, VLSI, p.131, 2012 [9] C.-H. Jan, et al, IEDM, p.44, 2012

Specifically, the alliance reports, for the first time, on high performance UTBB FD-SOI devices with a gate length (LG) of 20nm and BOX thickness (TBOX) of 25nm, featuring dual channel FETs (Si channel NFET and compressively strained SiGe channel PFET). Competitive effective current (Ieff) reaches 630μA/μm and 670μA/μm for NFET and PFET, respectively, at off current (Ioff) of 100nA/μm and Vdd of 0.9V.

Excellent electrostatics are obtained, demonstrating the scalability of these devices to14nm and beyond. Very low AVt (1.3mV•μm) of channel SiGe (cSiGe) PFET devices is reported for the first time. BTI was improved >20% vs a comparable bulk device. The paper concludes with evidence of continued scalability to 10nm 

and below.

“The effective current (Ieff), as a function of Ioff, is shown in Fig. 4. At Vdd=0.9V, NFET/PFET Ieff reach 630/670μA/μm at Ioff=100nA/μm, respectively. They are the best performing FDSOI CMOS devices reported so far, featuring non-strained Si channel NFET and strained SiGe channel PFET.”

7.3 Innovative ESD protections for UTBB FD-SOI Technology (STMicroelectronics, IMEP-LAHC)

ESD (electrostatic discharge) protection is often cited as a challenge in FD-SOI, and the ESD devices are typically put into a “hybrid” section of the chip, where the top silicon and insulator are etched away exposing the “bulk” silicon base wafer. In this paper, however, the ST-IMEP team presented FD-SOI ESD protection devices that achieve “remarkable performance in terms of leakage current and triggering control.” They demonstrate “ultra-low leakage current below 0.1 pA/μm and adjustable triggering (1.1V < Vt1 < 2.6V) capability. These devices rely on gate-controlled injection barriers and match the 28nm UTBB-FDSOI ESD design window by triggering before the nominal breakdown voltage of digital core MOS transistors.”

7.4 Comparison of Self-Heating Effect (SHE) in Short-Channel Bulk and Ultra-Thin BOX SOI MOSFETs: Impacts of Doped Well, Ambient Temperature, and SOI/BOX Thicknesses on SHE (Keio University, AIST)

This paper refutes those who say that the self-heating effect (SHE) is a bigger concern for SOI-based devices than bulk. The researchers investigated and compared bulk and SOI FETs including 6-nm ultra-thin (UT) BOX devices. They clarified, for the first time, that SHE is not negligible in bulk FETs, mainly due  to a decrease in the thermal conductivity of the more heavily doped well.  They found that the channel temperature of 6-nm UT BOX SOI FETs is close to that of bulk FETs at a chip temperature under operations. They then proposed a thermal-aware FD-SOI device design structure based on evaluated BOX/SOI thickness dependences of SHE. They concluded that SHEs in UTBB FETs with raised S/D and/or contact pitch scaling could be comparable to bulk FETs in deeply scaled nodes.

20.3 Gate-Last Integration on Planar FDSOI MOSFET: Impact of Mechanical Boosters and Channel Orientations  (Leti, ST)

This paper presents the industry’s first “gate last” (GL) results for FD-SOI, with ultra-thin silicon body (3-5nm) and BOX (25nm).  The team successfully fabricated transistors down to the 15nm gate length, with metal-last on high-k first (TiN/HfSiON). They thoroughly characterized the gate stack (reliability, work-function tuning on Equivalent Oxide Thickness EOT=0.85nm) and transport (hole mobility, Raccess) for different surface and channel orientations. They report excellent Ion, p=1020μA/μm at Ioff, p=100nA/μm at Vdd=0.9V supply voltage for <110> pMOS channel on (001) surface with in-situ boron doped SiGe Raised Source and Drain (RSD) and compressive CESL. They cite the high efficiency of the strain transfer into the ultra-thin channel (-1.5%), as evidenced by physical strain measurements by dark field holography.

12.4 UTSOI2: A Complete Physical Compact Model for UTBB and Independent Double Gate MOSFETs (ST, Leti)

Compact models of transistors and other elementary devices are used to predict the behavior of a design. As such, they are embedded in simulations like SPICE that designers run before actual manufacturing. In this paper, ST and Leti researchers presented a complete physical compact model called UTSOI2, which is dedicated to Ultra-Thin Body and Box FD-SOI technology, and is able to describe accurately independent double gate operation for sub-20nm nodes. It meets standard Quality and Robustness tests for circuit design applications.

12.5 Mobility in High-K Metal Gate UTBB-FDSOI Devices: From NEGF to TCAD Perspectives (Invited) (ST, Leti, U. Udine, Synopsys, Laboratoire Hubert Curien & Institut d’Optique, IBM)

This paper reviews important theoretical and experimental aspects of both electrostatics and channel mobility in High-K Metal Gate UTBB-FDSOI MOSFETs. With an eye toward optimization, the team presents a simulation chain, including advanced quantum solvers, and semi-empirical Technology Computer Assisted Design (TCAD) tools.

33.2 Suppression of Die-to-Die Delay Variability of Silicon on Thin Buried Oxide (SOTB) CMOS Circuits by Balanced P/N Drivability Control with Back-Bias for Ultralow-Voltage (0.4 V) Operation (LEAP, U. Tokyo)

SOTB is what Hitachi calls its flavor of FD-SOI.  The researchers point out that small-variability transistors like SOTB are effective for reducing the operation voltage (Vdd). This paper proposes the balanced n/p drivability for reducing the die-to-die delay variation by back bias for various circuits. Excellent delay variability reduction by this n/p balanced control is demonstrated at ultra-low Vdd of 0.4 V.

2.8: Co-Integration of InGaAs n- and SiGe p-MOSFETs into Digital CMOS Circuits Using Hybrid Dual-Channel ETXOI Substrate (IBM)

ETSOI is IBM’s flavor of FD-SOI, and this paper is about FD-SOI devices using high mobility material for boosting performance. The presenters “demonstrate for the first time on the same wafer and on the same device level a dense co-integration of co-planar nano-scaled SiGe p-FETs and InGaAs n-FETs UTBB FETs. This result is based on hybrid substrates containing extremely-thin SiGe and InGaAs layers on insulators (ETXOI) using double bonding.” They showed a) that it could be done; b) it’s viable hybrid high-mobility dual-channel CMOS; c) it still supports back-biasing for Vt tuning.

5.2 Surface Roughness Limited Mobility Modeling in Ultra-Thin SOI and Quantum Well III-V MOSFETs  (DIEGM – U. Udine)

As with the IBM paper (2.8) above, this paper is about FD-SOI devices using high mobility material for boosting performance. The abstract explains, “This paper presents a new model for surface roughness mobility accounting for the wave-function oxide penetration and can naturally deal with Hetero-Structure. Calibration with experiments in Si MOSFETs results in a r.m.s. value of the SR spectrum in close agreement with AFM and TEM measurements.” The simulated μSR in III-V UTB MOSFETs shows a weaker degradation at small channel thickness (T_w) than predicted by the T_6w law observed in UTB Si MOSFETs.

Please stay tuned for a subsequent ASN post that will cover the meeting’s SOI-FinFET, RF-SOI and advanced device papers.  (The papers themselves are typically available through the IEEE Xplore Digital Libary within a few months of the conference.)

An Update on the OpenPDK for IC Design (by Daniel Payne)

IC designers use EDA tools to implement their logical and physical design, and these tools require foundry-specific information for:

• Design Rule Checking (DRC)
• Layout Versus Schematic (LVS)
• Library Symbols
• Parasitic EXtraction (PEX)

This foundry information is called a Process Design Kit or PDK for short. Now put yourself in the place of the foundry or IDM, and you want to support EDA tools from multiple vendors like: Cadence Design Systems, Mentor Graphics, Synopsys, Silvaco and Tanner EDA. That adds up to a lot of QA and PDK development effort to support so many EDA vendors and tools. There has to be an easier way to create PDKs instead of one vendor at a time.




Read more at the original source

[mos-ak] [2nd announcement] Spring MOS-AK Workshop in London

Spring MOS-AK Workshop in London

Together with the workshop host, Prof. Bal Virdee, Londonmet, FIET MIEEE, and Prof. Mike Brinson, Londonmet, as well as Extended MOS-AK/GSA TPC Committee, we have pleasure to invite to the spring MOS-AK Workshop in London

Venue:

London Metropolitan University 

Graduate Centre

166-220 Holloway Road

London N7 8DB

Important Dates:

• Call for Papers - Dec 2013
  
• 2nd Announcement - Jan. 2014
  
• Final Workshop Program - Feb. 2014
  
• MOS-AK Workshop - March 28-29 2014

R&D topics to be covered include the following:

• Advances in semiconductor technologies and processing
  
• Compact Modeling (CM) of the electron devices
  
• Verilog-A language for CM standardization
  
• New CM techniques and extraction software
  
• CM of passive, active, sensors and actuators
  
• Emerging Devices, CMOS and SOI-based memory cells
  
• Microwave, RF device modeling, high voltage device modeling
  
• Nanoscale CMOS devices and circuits
  
• Technology R&D, DFY, DFT and IC Designs
  
• Foundry/Fabless Interface Strategies
  

Abstract Submission:

Authors should submit an abstract using on-line MOS-AK submission form (any related enquiries can be sent to abstract@mos-ak.org)

Postworkshop publications:

selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of Numerical Modelling: Electronic Networks, Devices and Fields

Extended MOS-AK/GSA Committee

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[mos-ak] [on-line publications] 6th International MOS-AK Workshop Washington DC Dec.11, 2013

Recent, 6th International MOS-AK/GSA Workshop on Dec.11, 2013 in Washington DC was organized to discuss SPICE/compact modeling and its standardization with a freewheeling session to review modeling activities of the CMC, IEEE EDS CMTC, NEEDS NanoHub and MOS-AK Groups. The workshop's presentations are available on-line at <http://www.mos-ak.org/washington_dc_2013/>

Please also distribute further information about next MOS-AK related events among all who are interested in the SPICE/compact modeling:

IWCM at DAC ASP Singapore (SG) Jan. 23, 2014 

http://www.ece.nus.edu.sg/stfpage/elehy/aspdac2014/

Q2 2014 MOS-AK London (UK) March'2014

http://www.mos-ak.org/london_2014/

MIXDES Lwow (UA) June 19-21, 2014

http://mixdes2014.lp.edu.ua/Mixdes3/tekst/view/special

Q3 MOS-AK at 44th ESSDERC / 40th ESSCIRC Venice (I) Sept. 26, 2014

http://www.mos-ak.org/venice_2014/

Already now, I am looking forward to meet you at one of our MOS-AK modeling events, soon.

-- with regards - wladek;
--

Arbeitskreis Modellierung von Systemen und Parameterextraktion 
Modeling of Systems and Parameter Extraction Working Group
--
Over two decades of Enabling Compact Modeling R&D Exchange

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http://www.mos-ak.org

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[mos-ak] SPICE Development Roadmap

The MOS-AK/GSA Modeling Working Group, a global compact modeling standardization forum, delivered its annual autumn compact modeling workshop on Sept. 20, 2013 as an integral part of the ESSDERC/ESSCIRC Conference in Bucharest (RO). The event received full sponsorship from leading industrial partners including Agilent Technologies, LFoundry and Microchip. More than 30 international academic researchers and modeling engineers attended two sessions to hear 12 technical compact modeling presentations and posters including the keynote by Larry Nagel.

The MOS-AK keynote speaker, Larry Nagel, delivered "SPICE in the Twenty-First Century" talk drawing a roadmap of future SPICE development directions. So how will SPICE evolve in the future?  [read more]

In the meantime please also visit <http://www.mos-ak.org/washington_dc_2013/> where we will continue the discussion of all compact/SPICE modeling topics.

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SISPAD 2014 1st Call for Papers

2014 International Conference on Simulation of Semiconductor Processes and Devices

September 9-11, 2014

Workshop, September 8

Mielparque Yokohama, Yokohama, Japan

The call for papers is also available on SISPAD2014 Web site. Deadline for submission of SISPAD abstracts: March 31, 2014


Any inquiries on submission should be sent to:

• Steering Chair:  Shinji Odanaka  (Osaka Univ)
• Conference Chair:  Nobuya Mori  (Osaka Univ)
• Program Chair:  Kenichiro Sonoda  (Renesas)
• Program Co-Chair:  Shigeyasu Uno  (Ritsumeikan Univ)

[read more...]

[mos-ak] [Final Program] 6th International MOS-AK/GSA Workshop Washington DC Dec.11, 2013

Final program of 6th International MOS-AK/GSA Workshop on Dec.11, 2013 in Washington DC is available online:

http://www.mos-ak.org/washington_dc_2013/

The program includes a freewheeling session organized to review modeling activities of the CMC, IEEE EDS CMTC, NEEDS NanoHub and MOS-AK Groups.

Event venue:

Embassy of Switzerland

2900 Cathedral Ave, NW,  

Washington, DC 20008 

USA 

Free On-line Workshop Registration is open, now.

Extended MOS-AK/GSA Committee:

• Wladek Grabinski, GMC Suisse; MOS-AK/GSA Group Manager
• Harrison Beasley, Technical WG Manager, GSA
  MOS-AK/GSA North America
• Chair: Pekka Ojala, Exar Corporation
• Co-Chair: Geoffrey Coram, Analog Devices
• Co-Chair: Prof. Jamal Deen, U.McMaster
• Co-Chair: Roberto Tinti, Agilent EEsof Division
  MOS-AK/GSA South America
• Chair: Prof. Gilson I Wirth; UFRGS; Brazil
• Co-Chair: Prof. Carlos Galup-Montor, UFSC; Brazil
• Co-Chair: Sergio Bampi, UFRGS, Brazil
• Co-Chair: Antonio Cerdeira Altuzarra, Cinvestav - IPN, Mexico
  MOS-AK/GSA Europe
• Chair: Ehrenfried Seebacher, AMS, Austria
  
• Co-Chair: Alexander Petr, XFab, Germany
  
• Co-Chair: Prof. Benjamin Iniguez, URV, Spain
  MOS-AK/GSA Asia/South Pacific
  
• Chair: Sadayuki Yoshitomi, Toshiba 
  
• Co-Chair: Xing Zhou, NTU Singapore    
  
• Co-Chair: A.B. Bhattacharyya, JIIT New Delhi

 

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2014 Workshop on Compact Modeling at techconnectworld.com

Abstracts due: December 13th, 2013

Synopsis: Compact Models (CMs) for circuit simulation have been at the heart of CAD tools for circuit design over the past decades, and are playing an ever increasingly important role in the nanometer system-on-chip (SOC) era. As the mainstream MOS technology is scaled into the nanometer regime, development of a truly physical and predictive compact model for circuit simulation that covers geometry, bias, temperature, DC, AC, RF, and noise characteristics becomes a major challenge.

Workshop on Compact Modeling (WCM) Is one of the first of its kind in bringing people in the CM field together. The objective of WCM is to create a truly open forum for discussion among experts in the field as well as feedback from technology developers, circuit designers, and CAD tool vendors. The topics cover all important aspects of compact model development and deployment, within the main theme - compact models for circuit simulation.

Symposium Chair: Professor Xing Zhou Nanyang Technological University, Singapore

[Call for Papers] IWCM 2014

Call for Papers IWCM 2014 

11th International Workshop on Compact Modeling 

January 23 (Thursday), 2014 

Suntec Singapore Convention and Exhibition Centre (Room 309)  

Scope: 
The workshop provides an opportunity for the discussion and the presentation of advances in modeling and simulation of integrated circuits.

Topics: 

• Compact modeling for all kinds of devices 
• Parameter extraction methodology and strategy 
• Circuit simulation techniques and platforms 

Abstract Submission:

Authors should submit a camera-ready abstract with 2 to 10 pages including figures for inclusion in the Workshop Proceedings, and send the electronic file in PDF or MS-Word format to mchan@ust.hk. Paper templates in Word format is downloadable from the ASP-DAC 2014 site. Deadline for the submission is December 15th, 2013. 

• Organization:
  Chair: Mansun Chan (Hong Kong University of Science and Technology, Hong Kong)
  Co-Chair: Hans Juergen Mattausch (Hiroshima University, Japan) 
• Committee members:
  T. Aikyou (STARC, Japan)
  Y. Cao (Arizona State University, USA)
  Jamel Deen (McMaster University, Canada)
  J. He (Peking University, China)
  Y. J. Park (Seoul National University, Korea)
  Zhiping Yu, (Tsinghua University, China)
  Xing Zhou (Nanyang Technology University, Singapore) 

Sponsor:
The University Grant Council of Hong Kong through the Area of Excellence Project (AOE/P-04/08)

Fee: Free admission

Contact: 
If you have any question, please contact  Mansun Chan

LETI Devices Workshop

The Churchill Hotel - 1914 Connecticut Ave. NW (across from the Hilton)

Washington D.C. 6-9 p.m on December 8, 2013

Inventing the future together: a stimulating discussion of our vision for silicon nanotechnologies in the next 10 years followed by a networking cocktail. Program is as follow:

• Introduction (10min)
  Jean-René Lequepeys; VP Silicon Components Division 
• Lithography cost-effective solutions for 1X nodes (15min)
  Serge Tedesco; Lithography Program Manager 
• 3D: Dream and reality (15 min)
  Mark Scannell; Senior Business Development Manager 
• High-performance and reliable resistive memories embedded in advanced logic CMOS technologies (15min)
  Barbara de Salvo; Advanced Memories Fellow
• M&NEMS platforms: an enabler for the next generation of sensors in consumer electronics (15min)
  Hugues Metras; VP Strategic Partnerships, North America
• CMOS technologies: our most power efficient solution today and our vision toward 10nm node and beyond (15 min)
  Maud Vinet; Advanced CMOS Manager

[read more...]

MIEL2014 Abstracts Deadline Extension

IEEE 29th International Conference on Microelectronics (MIEL 2014) is to be held on 11-14 May 2014 at the Serbian Academy of Science and Arts, Belgrade, Serbia. The extended submission deadline for 2-page extended abstracts of regular contributions had been set to 26th, but, due to many requests by authors, we will continue receiving the submissions by October 31st 2013.

More detailed information on MIEL 2014 can be found in the attached Call for Papers, as well as on the conference web site http://miel.elfak.ni.ac.rs/. We will be looking forward to receiving your submission and seeing you at our conference next year in May.

[read more...]

SISPAD Abstract Submission

2014 International Conference on Simulation of Semiconductor Processes and Devices

September 9 – 11, 2014

Workshop, September 8

Mielparque Yokohama, Yokohama, Japan

Deadline for submission of SISPAD abstract: March 1, 2014

Any inquiries on submission should be sent to:

• Program Chair:  Ken’ichiro Sonoda (Renesas)
• Program Co-Chair:  Shigeyasu Uno (Ritsumeikan Univ)

[read more...]

[mos-ak] note in the IEEE EDS REGIONAL AND CHAPTER NEWS

REGIONAL AND CHAPTER NEWS

ED Germany – by Joachim N. Burghartz 

The German Chapter of IEEE EDS sponsored the annual spring compact modeling workshop of the MOS-AK/GSA Modeling Working Group, a global compact modeling standardization forum, held April 11– 12, 2013. The meeting was supported by Prof. Doris Schmid-Landsiedel and the staff of the Institute for Technical Electronics, TUM, Munich, who is one of the local coordinators of the ED German Chapter. More than 30 international academic researchers and modeling engineers attended three sessions to listen to 12 technical compact modeling presentations. As in previous years this well-established effort has been coordinated by Wladek Grabinski, Switzerland. The workshop's three sessions focused on common compact modeling actions. Sessions included: (i) How to consolidate and build consistent simulation hierarchy at all levels of advanced TCAD numerical modeling; (ii) Compact/ SPICE modeling for Analog / Mixed Signal circuits; and (iii) Corner modeling and statistical simulations. The MOS-AK/GSA speakers were K.-W. Pieper (Infineon), M. Sylvester (MunEDA), B. Iñiguez (URV), I. Nickeleit (Agilent), L. Heiss (LTE, TUM); T. Schulz (Intel), C. Jungemann (RWTH), M. Brinson (London Metropolitan University), B.-Y. Nguyen (SOITEC), A. Kloes (THM), U. Monga (Intel), and M. Bucher (TUC). The event was accompanied by a series of the software/hardware demos by MOS-AK/GSA industrial partners: Agilent, MunEDA and Tanner EDA. The session technical and software/ hardware demo presentations are available for download at: <http:// www.mos-ak.org/munich_2013/>. 

[full text]

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OBip: Open Bipolar Workshop at BCTM in Bordeaux

Open Workshop on European Bipolar related projects: 

DOTSEVEN & RF2THz

Abstract: In Europe, a huge effort is actually undertaken to strengthen Europe's leading edge position in SiGe HBT technology and modeling as well as SiGe enabled mm-wave applications thanks to two European projects that are: DOTSEVEN which aims to achieve HBTs with cut-off frequencies (fmax) of around 700 GHz and RF2THz which aims at the establishment of a 300mm BiCMOS Silicon technology platform for emerging RF, mm-wave and THz consumer applications, as well as Si photonics integration. During this common workshop the main achievements of these projects will be presented.

Opening and Welcome (8:15 AM), Thomas Zimmer, University  Bordeaux 1

Session 1: Technology (8:30 - 10:30 AM)
Alexander Fox, IHP (8:30 - 9:10 AM)
   SiGe HBT Technology Development in the DOTSEVEN  Project
Pascal Chevalier, ST Microelectronics (9:10 - 9:50 AM)
   A 55-nm BiCMOS Platform for Optical and Millimeter-Wave  Systems-on-Chip
Dieter Knoll, IHP (9:50 – 10:30 AM)
   BiCMOS integration of photonic components
Coffee break
Session 2: Modelling and Characterization (11:00 AM – 1:00 PM)
Andreas Pawlak, Univ. of Dresden (11:00 – 11:40 AM)
   Latest developments of HICUM/L2 for mm-wave applications
Bertrand Ardouin, XMOD Technologies (11:40 – 12:20 AM)
   Tools and environment for Sub-THz circuit design
Sebastien Fregonese, CNRS (12:20 AM – 1:00 PM)
   Electro-Thermal Device Characterization & Modelling
Lunch break
Session 3: Design and demonstrator (2:00 – 4:00 PM)
Marco Spirito, University of Delft (2:00 – 2:40 PM)
   Building blocks and system architecture for mm-wave imaging radar
Olivier Tesson, NXP (2:40 – 3:20 PM)
   Passive integration and Packaging for mm-wave applications
Wolfgang Templ, Alcatel Lucent (3:20 – 4:00 PM)
   Application Scenarios from RF2THz

4:00: End of the Open Bipolar Workshop OBip

[read more: 3rd Day Workshop: Special European Dot 5/Dot 7 Workshop]

[mos-ak] Call for Papers] 6th International MOS-AK/GSA Workshop Dec. 11, 2013 Washington DC

Together with the Organizing Committee and Extended MOS-AK/GSA TPC Committee, we have pleasure to invite to the 6th International MOS-AK/GSA Workshop Dec. 11, 2013 Washington DC. The specific workshop goal will be to classify the most important directions for the future development of the electron device models, not limiting the discussion to compact models, but including physical, analytical and numerical models, to clearly identify areas that need further research and possible contact points between the different modeling domains (Technology TCAD, SPICE/Verilog-A standardization, advanced IC designs) . A freewheeling session will be also organized to review modeling activities of the CMC, NEEDS NanoHub and MOS-AK Groups.

Topics to be covered include the following:

• Advances in semiconductor technologies and processing
  
• Compact Modeling (CM) of the electron devices
  
• Verilog-A language for CM standardization
  
• New CM techniques and extraction software
  
• CM of passive, active, sensors and actuators
  
• Emerging Devices, CMOS and SOI-based memory cells
  
• Microwave, RF device modeling, high voltage device modeling
  
• Nanoscale CMOS devices and circuits
  
• Technology R&D, DFY, DFT and IC Designs
  
• Foundry/Fabless Interface Strategies
  

Speakers provisionary list (in alphabetic order)

• Keith Green, TI, CMC Chair (US)
  
• Benjamin Iniguez, URV (SP)
  
• Eric Keiter, Xyce Team, Sandia (US) 
  
• Luca Larcher, Uni. Modena (I)
  
• Mark Lundstrom, NEEDS, NanoHub (US)
  
• Michael Shur, RPI (US)
  
• Sadayuki Yoshitomi, Toshiba (J)
  

In the terms of participation, intending participants and authors should also note the following dates: 

• Call for Papers - Sept. 2013
  
• 2nd Announcement - Oct 2013
  
• Final Workshop Program - Nov. 2013
  
• MOS-AK/GSA Workshop - Dec. 11, 2013
  

Free early registration: <http://www.mos-ak.org/washington_dc_2013/registration.php>

Abstract on-line submission: <http://www.mos-ak.org/washington_dc_2013/abstracts.php> 

Further details and updates: <http://www.mos-ak.org/washington_dc_2013/> 

Email contact: <workshops@mos-ak.org> 

- with regards - WG (for the MOS-AK/GSA Committee) 

===

Arbeitskreis Modellierung von Systemen und Parameterextraktion 

Modeling of Systems and Parameter Extraction Working Group 
http://mos-ak.org/

===

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Semiconductor Device Characterization Intern Job

Semiconductor Device Characterization Engineer jobs

Characterization Intern Job Micron 70 reviews - Boise, ID Successful candidates for this position will have:. Experience with Shell Scripts (Perl, Unix, Batch, Python, etc.).... Micron - Aug 20

Indeed: one search. all jobs. 177 Broad Street - Stamford, CT 06901

Semiconductor Device Characterization Engineer jobs

Semiconductor Device Characterization Engineer jobs

Senior/Staff Characterization Engineer Qualcomm  90 reviews - San Jose, CA Interacts with other groups such as Design, Process, System, Reliability, and FA. 5+ years of related hands-on industrial experience.... Qualcomm - 5:25 AM Senior/Staff Device Physics and Sensor Modeling Engineer Qualcomm 90 reviews - San Jose, CA 5+ years of related hands-on industrial design experience. Hands-on experience with device physics, device process, device characterization, and systems.... Qualcomm - 5:25 AM SEMICONDUCTOR R & D PROCESS IMPROVEMENT ENGR IBM CORPORATION 1,821 reviews - Somers, NY Possess working knowledge of semiconductor device development processes. Semiconductor Research and Development Process Improvement Engineer, IBM Corporation,... New York Times - 8:27 AM

Indeed: one search. all jobs. 177 Broad Street - Stamford, CT 06901

Fwd: 4 new Semiconductor Device Characterization Engineer jobs

Semiconductor Device Characterization Engineer jobs

---

4 new jobs found

Applications Engineer Intersil 11 reviews - Milpitas, CA Knowledge of analog and mixed signal board level design including PCB layout guidelines a strong plus. Knowledge of both analog and digital video interface... Intersil - 11:04 PM Process Engineer GLOBALFOUNDRIES - Malta, NY Technology related Bachelor's degree with 6 years experience ;. or Master's degree plus 5 years experience in process technology development area;.... GLOBALFOUNDRIES - 7:22 PM Reliability DA Engineer - EM/SH/ESD - 717531 Intel 325 reviews - Hillsboro, OR Experience would be obtained through your educational level research and/or relevant job/internship experiences.... Intel - 2:45 PM Sr Engineer - CMOS 5Gb/s+ (AMD-26317) Quantum Solution - Sunnyvale, CA Excellent proficiency of Cadence's custom IC design environment, analog/mixed signal circuit simulation (Spectre, Hspice, Ocean scripting, ).... Quantum Solution - 4:53 AM

View jobs: since yesterday - for last 7 days - all jobs

Indeed: one search. all jobs. 177 Broad Street - Stamford, CT 06901

[mos-ak] [Final Program] 11th MOS-AK ESSDERC ESSCIRC Workshop with the keynote speaker Larry Nagel

Together with Prof. Andrei Vladimirescu, R&D Scientific Coordinator, the Organizing Committee and Extended MOS-AK/GSA TPC Committee, we have pleasure to invite to the 11th consecutive MOS-AK ESSDERC ESSCIRC Workshop on Sept. 20, 2013 in Bucharest (RO). The event will open next decade of enabling compact modeling R&D exchange.  

The final workshop program as well as all further details and updates are on-line: <http://www.mos-ak.org/bucharest/> 

- with regards - WG (for the MOS-AK/GSA Committee) 

MOS-AK Workshop Program

9:00 - 12:00	Morning Session - Chair: Prof. Andrei Vladimirescu, ISEP (F); UCB (USA)
O_1	Welcome and Workshop Opening W. Grabinski MOS-AK Group (EU)
T_2	SPICE - MOS-AK Keynote Larry Nagel Omega Enterprises Consulting (USA)
T_3	NGSPICE: recent progresses and future plans Paolo Nenzi*, Francesco Lannutti*, Robert Larice**, Holger Vogt**, Dietmar Warning** *DIET - Sapienza University of Roma (I), ** NGSPICE Development Team
T_4	KCL and Linear/NonLinear Separation in NGSPICE Francesco Lannutti DIET - Sapienza University of Roma (I) and NGSPICE Development Team
	Coffee Break
T_5	Modeling Junction Less FETs Jean-Michel Sallese, Farzan Jazaeri, Lucian Barbut EPFL (CH)
T_6	HiSIM-Compact Modeling Framework Hans Juergen Mattausch Uni. Hiroshima (J)
P_7	The Correct Account of Nonzero Differential Conductance in the Saturation Regime in the MOSFET Compact Model Valentin Turin*, Gennady Zebrev**, Sergey Makarov***, Benjamin Iniguez****, and Michael Shur***** *State University-ESPC (RU),**MEPHI (RU),***SYMICA Inc (RU),****URV (SP),*****RPI (USA)
12:00 -13:00	Lunch Break
13:00 -16:00	Afternoon Session - Chair: W. Grabinski, MOS-AK Group
T_8	State of the Art Modeling of Passive CMOS Components Bernd Landgraf  Infineon Technologies (A)
T_9	Compact I-V Model of Amorphous Oxide TFTs Benjamin Iniguez*,Alejandra Castro-Carranza* , Muthupandian Cheralathan* , Slobodan Mijalkovic**, Pedro Barquinha***, Elvira Fortunato***, Rodrigo Martins***,Magali Estrada****, and Antonio Cerdeira**** *URV (SP), **Silvaco Ltd (UK), ***UNL(P), ****CINVESTAV (MEX)
	Coffee Break
T_10	Three-Dimensional Electro-Thermal Circuit Model of Power Super-Junction MOSFET Aleš Chvála, Daniel Donoval, Juraj Marek, Patrik Príbytný and Marián Molnár Institute of Electronics and Photonics, Slovak University of Technology in Bratislava (SK)
T_11	A Close Comparison of Silicon and Silicon Carbide Double Gate JFETs Matthias Bucher, Rupendra Sharma Technical University of Crete, Chania, (GR)
T_12	Towards wide-frequency substrate model of advanced FDSOI MOSFET Sergej Makovejev, Valeriya Kilchytska, Jean-Pierre Raskin, Denis Flandre UCL (B)
16:00	End of the MOS-AK Workshop

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[repost nanobuff] On compact modeling

Posted on June 27, 2013 on nanobuff

"While the modeling industry is full of software solutions for all sorts of things in the operation of electronics from the very low to the very high level, there seems to be very sparse tools for simulating radiation effects. This would be normal if there was little interest or public research on the subject, but that is not the case. The models are out there, most of the basic concepts have been examined lots of decades ago, so what is stopping the industry? I really don’t know and I will not even try to answer.

Having said that, I would also like to state that compact modelling, in the case of radiation effects, is at least beneath me. I recently found this old compact modelling project. It is like a plugin to the Silvaco software. How would a compact modelling platform work in the ever-reducing dimensions of today? Things get fairly uncertain below 0.1 µm gate lengths. We need 3D, we need quantum models etc. just for the operation. And for the radiation part? That is now a materials science problem, I guess. And if you decide to go Monte Carlo, that’s even more demanding. The problem seems to be a “chicken and egg” one. We need more processing power to be able to simulate our next generation electronics that will give us more processing power."

[Leave a Reply]

Third Berkeley Symposium on Energy Efficient Electronic Systems

Time: October 28 - 29, 2013
Place: Sutardja Dai Hall, UCB, California, USA

Message from Symposium Organizers

Once again, we look forward to hosting another Berkeley Symposium on Energy Efficient Electronic Systems, a forum that we founded in 2009. Biennially, we bring together researchers who are working on breakthrough improvements in energy efficiency for information processing systems. Our goal is that the Symposium continue to be a venue for the attendees to gain an integrated perspective of the challenges and advances in this domain of technology through sessions that cover the entire food chain, from devices to systems. As in the two previous symposia, we expect that the academic setting of UC Berkeley will encourage open exchanges of ideas, and foster closer cooperation and collaborations among the researchers.

For the first time, we welcome IEEE Electronic Devices Society as a technical co-sponsor. Also new, the 2013 Organizing Committee is issuing a Call for Papers. These changes are intended to broaden participation at the Symposium, thereby furthering the Symposium's goal of fostering information exchanges and collaborations.

We look forward to seeing you at the 3rd Berkeley Symposium on Energy Efficient Electronic Systems.

Eli Yablonovitch, Co-Chair, Organizing Committee
Jeffrey Bokor, Co-Chair, Organizing Committee

[Symposium Link]

URSI-C Commission Workshop (Kawasaki)

Theme: "Simulation Techniques for wireless communication integrated circuit design" 

Sponsorship:

• URSI-C committee  

Sponsored by:

• IEEE MTT-S Japan Chapter 
• IEEE AP-S Japan Chapter 
• IEEE VT-S Japan Chapter 
• IEEE SSC-S Japan Chapter 

Date and time: Friday, 12:30 to 16:30, July 05, 2013
Location:  Toshiba Science Museum (directions from Komukaitoshiba town)
Entry fee: Free

Program
12:15 - 12:30 Reception
12:30 - 13:15 Toshiba Science Museum tour
13:30 - 13:40 Opening Remarks Masahiro Morikura (Kyoto University)
13:40 - 14:20 "High frequency modeling of the MOSFET, including the process variation" Yoshitomi Sadayuki (Toshiba)
14:20 - 15:00 "Challenges and Solutions for RFIC Realization"  Sugaya Hidehiko (Cadence Japan)
15:00 - 15:10 Break (10 minutes)
15:10 - 15:50 "Methodology for substrate coupling analysis with high frequency accuracy" Sotiris Bantas (Helic, Inc.)
15:50 - 16:30 "Behavioral technology of RF transceiver circuit" Takahiro Kikuchi (Agilent Technologies)
16:30 Closing
17:30 - social gathering

[read more...]