[Final Program] EUROSOI 2014, Tarragona, Catalonia, Spain; January 27-29, 2014

The 10th Workshop of the Thematic Network
on Silicon on Insulator Technology, Devices and Circuits 

(EUROSOI 2014) 

Tarragona, Catalonia, Spain 

January 27-29, 2014 

The EUROSOI Workshop is an international forum to promote interaction and exchangesbetween research groups and industrial partners involved in SOI activities all over the world. Following the lively experience of the previous meetings in Granada (2005), Grenoble (2006), Leuven (2007), Cork (2008), Gšteborg (2009), Grenoble (2010), Granada (2011), Montpellier (2012), Paris (2013), EUROSOI 2014 will be held in Tarragona, Catalonia, Spain, and will include a short course program, oral and poster sessions, outstanding key-note presentations, as well as ample rooms for informal discussions. EUROSOI covers recent progress in SOI technologies and will be of interest to materials and device scientists, as well as to process, circuits and applications oriented engineers.

Monday, January 27, 2014

8:30 REGISTRATION
9:05-9:20 SHORT COURSE OPENING
9:20-11:00 PART 1 - EDS MINI-COLLOQUIUM ON SOI TECHNOLOGY 
9:20-10:10 "Process Challenges for Advanced Ge CMOS Technologies" Cor Claeys (IMEC, Leuven, Belgium)
10:10-11.00 "From Floating-Body Memory to Unified Memory on SOI" Sorin Cristoloveanu (INPG, Grenoble, France)
11:00-11:30 COFFEE BREAK
11:30-12:20 "Fabrication Challenges for sub-10 nm Technology nodes" Michael Ostling (KTH, Stockholm, Sweden)
12:20-13:00 "ESD protection of FD and MuG SOI CMOS Chips" Dimitris Ioannou (George Mason University, Fairfax, VA, USA)
13:00-14:30 LUNCH
14:30-15:50 Part 2 -EUROSOI TUTORIAL 
14:30-15:20 "Advanced SOI MOSFET architectures" Jason Woo (UCLA, CA, USA)
15:20-16:00 "SOI CMOS sensors, transistors and circuits for ultra-low-power and harsh environment applications" Denis Flandre (UCL, Louvain-la-Neuve, Belgium)
16:00-16:30 COFFEE BREAK
16:30-18:00 SOI MOSFET CHARACTERIZATION 
16:30-17:20 "On the threshold voltage and interface coupling in advanced SOI MOSFETs" Tamara Rudenko (ISP, Kyiv, Ukraine)
17:20-18:00 "From SOI MOSFET to Spin MOSFET: a modeling approach" Viktor Sverdlov (Tu-Wien, Austria)
20:30 EUROSOI RECEPTION

Tuesday January 28, 2014 

8:15 REGISTRATION
8:45-9:00 OPENING
9:00-11:00 PLENARY SESSIONS 
9:00-9:40 "Taking the next step on advanced HKMG SOI technologies -from 32 nm PD SOIvolume production to 20/28 FD SOI and beyond" Manfred Horstmann (Globalfoundries, Dresden, Germany) invited talk
9:40-10:20 INVITED TALK 
Heike Riel (IBM Research, Zurich) -invited talk
10:20-11:00 "Beyond Si CMOS: Benefits and Challenges " Rafael Rios (Intel, Portland OR, USA) -invited talk
11:00-11:20 COFFEE BREAK
11:20-13:00 SOI MATERIALS TECHNOLOGY AND CHARACTERIZATION 
11:20-11:40 Process and performance of Copper TSVs Lado Filipovic et al.
11:40-12:00 Increasing mobility and spin lifetime with shear strain in thin silicon films Dmitri Osintsev et al.
12:00-12:20 A Comparative Study of Variability of RTN Power Spectral Densities in Bulk and SOIMOSFETs  Louis Gerrer et al.
12:20-12:40 Low temperature noise spectroscopy of p-channel SOI FinFETs Bogdan Cretu et al.
12:40-13:00 Channel Length Influence on the Low-Frequency Noise of Strained 45o Rotated Triple Gate SOI nFinFETs Marcio Alves Sodre de Souza et al.
13:20-14:10 LUNCH
14:10-15:50 SOI MOSFET TECHNOLOGY 
14:10-14:30 Impact of S/D doping profile into electrical properties in nanoscaled UTB2SOI  devices Carlos Sampdero et al.
14:30-14:50 TCAD investigation on a formal Neuron device in 28nm UTBB FDSOI technology Philippe Galy et al.
14:50-15-10 Dual ground plane for high-voltage MOSFET in UTBB FDSOI Technology Antoine Litty et al.
15:10-15:30 Trigate NanoWire MOSFETs Analog Figures of Merit Kilchytska, Valeriya et al.
15:30-15:50 Electrostatically-doped SL FET optimized to meet all the ITRS power targetsat V_DD=0.4 V Elena Gnani et al.
15:50-16:00 COFFEE BREAK
16:00-17:20 SOI MOSFET CHARACTERIZATION 
16:00-16:20 Enhanced Dynamic Threshold Voltage UTBB SOI nMOSFETs Katia Sasaki et al.
16:20-16:40 Parasitic bipolar effect in advanced FD SOI MOSFETs: experimental evidence andgain extraction Fanyu Liu et al.
16:40-17:00 Impact of Lateral Fin-Width Non-Uniformity of FinFETs Clarissa Prawoto et al.
17:00-17:20 Surface effects on split C-V measurements on SOI wafers Luca Pirro et al.
17:20-17:40 Impact of Self-Heating on UTB MOSFET ParametersS ergej Makovejev at al.
17:40-18:00 POSTER BRIEFING (3 MIN EACH) 
18:00-19:40 POSTER SESSION 
Subthreshold Behavior of the PD SOI NMOS Device Considering BJT and DIBL Effects James Kuo et al.
Investigation of Statistical Effects on Reliability of SOI FinFETs Including Sidewall Crystal Orientation Salvatore Amoroso et al.
Powering the More than Moore Electronics with i-MOSLining Zhang et al.
Analysis of Short-Channel Effect in SOTB-MOSFET for Ultra-Low Power Applications Hidenori Miyamoto et al.
2D Analytical Modeling of the Trap-Assisted-Tunneling Current in Double-GateTunnel-FETs Michael Graef et al.
Improved Compact Current Model for FinFETs Based in a New Geometric Approach Arianne Pereira et al.
Capability of the IDS Analytical Model on Predicting the Diamond Variability by Usingthe F-Test Statistic Evaluation Salvador Gimenez et al.
An appraise of the sources of electrical parameters variation in DGMOS Rodrigo Picos et al.
An analytical model for the inversion charge distribution in GAA MOSFETs with rounded corners Francisco Ruiz et al.
The Negative World-line Holding Bias Effect on the Retention Time in FBRAMs Sara Santos et al.
20:30 GALA DINNER

Wednesday January 29, 2014 

8:30-10:30 SOI MOSFET MODELLING 
8:30-8:50 Comprehensive Low-Field Mobility Modeling in Nano-Scaled SOI Channels Zlatan Stanojevic et al.
8:50-9:10 A comprehensive DC current model to describe FinFET self-heating effects Benito Gonz‡lez et al.
9:10-9:30 Channel-Length Impact on Supercoupling Effect in FD-MOSFETs Carlos Navarro et al.
9:30-9:50 Substrate Effect on Threshold Voltage of long and short channel UTBB SOI nMOSFETs Joao Martino et al.
9:50-10:10 In depth characterization of electron transport in 14nm FD-SOI nMOS devices Minju Shin et al.
10:10-10:30 Role of the gate in ballistic nanowire SOI MOSFET Anurag Mangla et al.
10:30-10:50 COFFEE BREAK
10:50-13:10 CIRCUITS, MEMORIES AND SENSORS 
10:50-11:30 "Future of Multi-gate CMOS Technology" Hiroshi Iwai (University of Tokyo, Japan)
11:30-11:50 Impact of SEU on Bulk and FDSOI CMOS SRAM Walter Enrique Calienes Bartra et al.
11:50-12:10 Mechanical Characterization and Modelling of Lorentz Force Based MEMS Magnetic Field Sensors Petros Gkotsis et al.
12:10-12:30 Performance of Source-Follower Buffers Implemented with Junctionless Nanowire nMOS Transistors Michelly Souza et al.
12:30-12.50 PMOSFET-based Pressure Sensors in FD SOI Technology Benoit Olbrechts et al.
12:50-13:10 Performance of Common-Source current mirrors with asymmetric self-cascode SOInMOSFETs  Rafael Assalti et al.
13:10-14:20 LUNCH
14:20-16:10 BEYOND CMOS: NANOWIRES AND JUNCTIONLESS TRANSISTORS 
14:20-15:00 "2D semiconductor channels for ultimate thickness scaling and other versatile applications" Athanasios Dimoulas (IMS, Demokritos, Athens, Greece)
15:00-15:20 A way to solve Poisson equation en cylindrical coordinates to obtain a compact model for Junctionless Gate All Around MOSFET Franois Lime et al.
15:20-15:40 Explicit analytical charge and capacitance models for Junctionless Surrounding GateTransistors  Oana Moldovan et al.
15:40-16:00 Performance Evaluation of Stacked Gate-All-Around MOSFETs Meng-Hsueh Chiang et al.
16:00-16:20 Modeling of Quantization Effects in Nanoscale DG Junctionless MOSFETs Thomas Holtij et al.
16:20-16:30 COFFEE BREAK
16:30-16:50 BEYOND CMOS (TFETs) 
16:30-16:50 Heterojunction TFET inverters providing better performance than multi-gate CMOS at sub 0.3V Vdd Elena Gnani et al.
16:50-17:10 Transport mechanism influence on Vertical Nanowire-TFET analog performance as a function of temperature Paula Agopian et al.
17:10-17:30 3D Modeling of Direct Band-to-Band Tunneling in Nanowire TFETs. Lidija Filipovic et al.
17:30-17:50 Influence of the gate oxide thickness on the Analog Performance of vertical Nanowire-Tunnel FETs with Ge Source Felipe Neves et al.
17:50-18:10 Influence of a precisely positioned channel dopant on the performance of gate-allaround Si nanowire transistor: a full 3D NEGF simulation study Vihar Georgiev et al.
18:10-18:20 CONCLUSIONS AND ANNOUNCEMENTS