Tuesday, February 4, 2014

[Call for Papers] SISPAD2014


This is a call for papers for the 2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD2014), to be held September 9-11, 2014, in Yokohama, Japan. This conference provides an opportunity for the presentation and discussion of the latest advances in modeling and simulation of semiconductor devices, processes, and equipment for integrated circuits.

Abstract submission deadline is March 31, 2014.

Two companion workshops will run concurrently prior to the start of the conference on Monday 8th September 2014:

  • Workshop 1: Compact Modeling -Enabling Better Insight of Device Features-
    Organizer: Mitiko Miura-Mattausch (Hiroshima University)
  • Workshop 2: Carrier Transport in Nano-MOS Transistors: Theory and Experiments(tentative)
    Organizer: Hideaki Tsuchiya (Kobe University) and Yoshinari Kamakura (Osaka University)

Plenary Speakers:

  • Augusto Benvenuti (Micron Technology)
    Current status and future prospects of non-volatile memory modeling
  • Massimo V. Fischetti (University of Texas at Dallas)
    Physics of electronic transport in low-dimensionality materials forfuture FETs
  • Kimimori Hamada (Toyota Motor Corporation)
    TCAD challenge on development of power semiconductor devices for automotive applications

Invited Speakers:

  • Mario Ancona (Naval Research Laboratory)
    Nonlinear thermoelectroelastic simulation of III-N devices
  • Asen Asenov (University of Glasgow)
    Progress in the simulation of time dependent statistical variability in nano CMOS transistors
  • Jean-Pierre Colinge (Taiwan Semiconductor Manufacturing Company)
    Nanowire transistors: pushing Moore's law to the limit
  • Tibor Grasser (Vienna University of Technology)
    Advanced modeling of charge trapping: RTN, 1/f noise, SILC, and BTI
  • Kohji Mitsubayashi (Tokyo Medical and Dental University)
    Novel biosensing devices for medical applications
  • Christian Sandow (Infineon Technologies)
    Exploring the limits of the safe operation area of power semiconductor devices
  • Mark Stettler (Intel Corporation)
    Device and process modeling: 20 years at Intel's other fab

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