[Book] Low-power HF Microelectronics: a unified approach

Low-power HF Microelectronics: a unified approach 

ISBN: 9780852968741 e-ISBN: 9781849193610

Editor: Gerson A. S. Machado

Department of Electronic Engineering

Imperial College of Science, Technology and Medicine

London, UK

Front Matter
1 Low-power HF microelectronics: a unified approach
Part 1: Process technology
2 Device structures and device simulation techniques
3 Stanford's ultra-low-power CMOS technology and applications
4 SOI technology
5 Radiation effects on ICs and a mixed analog CMOS-NPN-PJFET-on-insulator technology
Part 2: Device modelling/characterisation and circuit simulation
6 Modelling and characterisation of GaAs devices
7 The EKV Model: a MOST Model Dedicated to Low-Current and Low-Voltage Analogue Circuit Design and Simulation
8 Non-linear dynamic modelling of RF bipolar transistors
9 APLAC - object-oriented circuit simulator and design tool
10 Noise coupling in mixed-signal ASICs
Part 3: Reliability and test
11 Robust design and reliability analysis
12 Dynamic reliability of systems
13 Fault modelling and simulation for the test of integrated analog and mixed-signal circuits
Part 4: Circuit and system design methodology
14 High-speed and low-power techniques in CMOS and BiCMOS
15 Ultra-low-power digital design
16 Matched delay technique for high-speed digital design
17 Statistical design and optimisation for high-yield BiCMOS analog circuits
18 Design considerations for high-speed amplifiers using complementary BJTs
19 S2I techniques for analog sampled-data signal processing
20 Design of wireless portable systems
21 Low-power radio-frequency ICs and system architectures for portable communications
22 Analog and digital CMOS design for spread-spectrum wireless communications
23 Design considerations for BJT active mixers
24 Distortion in short channel FET circuits
25 Intelligent sensor systems and smart sensors: concepts, focus points and technology
26 Intelligent sensor systems and smart sensors: applications
Back Matter

Publication stats: 1260 Reads

1260 Reads: Open-source circuit simulation tools for RF compact semiconductor device modelling

Article · Sep 2014 · International Journal of Numerical Modelling Electronic Networks Devices and Fields

[paper] Impact of technology scaling on analog and RF performance of SOI–TFET

Impact of technology scaling on analog and RF performance of SOI–TFET

P Kumari, S Dash and G P Mishra
Advances in Natural Sciences: Nanoscience and Nanotechnology, Volume 6, Number 4 

Published 9 October 2015

Abstract

This paper presents both the analytical and simulation study of analog and RF performance for single gate semiconductor on insulator tunnel field effect transistor in an extensive manner. Here 2D drain current model has been developed using initial and final tunneling length of band-to-band process. The investigation is further extended to the quantitative and comprehensive analysis of analog parameters such as surface potential, electric field, tunneling path, and transfer characteristics of the device. The impact of scaling of gate oxide thickness and silicon body thickness on the electrostatic and RF performance of the device is discussed. The analytical model results are validated with TCAD Sentaurus device simulation results [read more...]

Citations
[1] Extensive electrostatic investigation of workfunction-modulated SOI tunnel FETs Subhrasmita Panda et al  2016 Journal of Computational Electronics 15 1326
[2] S. Sahoo et al  2016 337
[3] A comprehensive investigation of silicon film thickness (T SI) of nanoscale DG TFET for low power applications Rajeev Ranjan et al  2016 Advances in Natural Sciences: Nanoscience and Nanotechnology 7 03500
[4] A complete analytical potential based solution for a 4H-SiC MOSFET in nanoscale M K Yadav et al  2016 Advances in Natural Sciences: Nanoscience and Nanotechnology 7 025011
[5] S. Dash et al  2015 447
   

Writing a science/tech book, is it that hard?

Writing a science/tech book, is it that hard?

As a microwave engineer Errikos Lourandakis, PhD, a senior R&D engineer at Helic Inc., started with RF device characterization while working on his PhD. He got fascinated about it and gradually devoted much of his time in the lab (see his lab pic below), though RF and Microwave Measurements were just a vehicle for microwave circuit design that was his actual PhD topic. After 10+ years in academia and industry, recently he has also published his new book "On-Wafer Microwave Measurements and De-embedding"

Errikos' RF and mm-Wave Measurement Lab

Is it worth it? [read more...]

[paper] Small-Signal Characterization and Modeling of 55 nm SiGe BiCMOS HBT up to 325 GHz

Small-Signal Characterization and Modeling of 55 nm SiGe BiCMOS HBT up to 325GHz

Marina Deng^a, Thomas Quémerais^b, Simon Bouvot^a, ^b, Daniel Gloria^b, Pascal Chevalier^b

Sylvie Lépilliet^a, François Danneville^a, Gilles Dambrine^a

^aIEMN UMR CNRS 8520, University of Lille, Avenue Poincaré, CS60069, 

59652 Villeneuve-d’Ascq Cedex, France

^bSTMicroelectronics, 850 rue Jean Monnet, 38926 Crolles, France

Highlights

• The SiGe HBT full S-parameters from 250MHz to 325GHz under multiple bias conditions are presented for the first time.
• Standard calibration and de-embedding techniques are used and remained valid up to 325GHz thanks to a reduction of the test structures dimensions.
• A simple and accurate small-signal electrical model was extracted and compared with measurements up to 325GHz.

Received 19 September 2016, Revised 18 November 2016, Accepted 21 November 2016, Available online 22 November 2016 [read more...]

http://dx.doi.org/10.1016/j.sse.2016.11.012

[Summer Tutorial] Verified Measurements for Successful Device Models

 Verified Measurements for Successful Device Models 

 at IHP in Frankfurt (Oder), June 15-17, 2016 

Good electronic device modeling results depend directly on reliable, qualified and verified measurements. It is a known fact that problems with device models are – to a big part – rather due to measurement problems. Within the measurement chain of DC, Impedance (CV), S-Parameter, Nonlinear RF, and Noise, there are several challenges to overcome like device self-heating, contact resistance, max. applicable RF power, calibration, de-embedding etc.

IHP Summer Tutorial will take place at IHP in Frankfurt (Oder), June 15-17, 2016. It will cover in detail all these measurement domains, will explain the setups, the data verification methods, the traps to be avoided, and give best-practice recommendations and examples. It will be enhanced by live measurements in IHP’s measurement labs.

As a wrap-up, an introduction into device modeling, applying the qualified and verified measurements, will be given at the end.

Who should attend: Semiconductor manufacturing and measurement engineers, device modeling engineers, scientists and students working/interested in measurement techniques.

[Course Schedule]

[Incize] Senior Semiconductor R&D Engineer

Incize is recruiting a senior semiconductor R&D engineer for a three-year research project. The project aims to develop an innovative semiconductor characterization technique that is of great interest for the semiconductor industry.

What Incize offers:

• Permanent contract
• Infinite opportunities to learn
• Friendly and flexible environment
• Competitive salary

What Incize requires:

• PhD in physics, electronics or material science
• Knowledge of semiconductor physics, microwave theory, optics and their applications
• Experience  in  designing  and  running  experiments  in  microwave  and  optics domains
• Experience in TCAD and ADS simulations
• Clean-room experience is an advantage
• Passion for research and innovation
• 2-3 years of experience in R&D after PhD

Your Responsibilities

• Development of a new characterization method and its theoretical background
• Planning and execution of experiments
• Numerical TCAD and ADS simulations
• Literature search

How to apply

Please send your CV, a list of publications and a cover letter to info@incize.com with the subject line job_RD01_2016_lastname. References should be provided upon request.

About Incize

Incize provides characterization and modelling services for semiconductor foundries and fabless companies. It is a spin-off from Université catholique de Louvain and is based in Louvain-la-Neuve, Belgium. Visit www.incize.com to find out more.

www.incize.com

Chemin du Cyclotron, 6

B-1348 Louvain-la-Neuve, Belgium

T: +32 10 39 22 60

F: +32 10 39 20 01

[video] How to Model RF Passive Components: Capacitors and Resistors

This video explains and demonstrates a method to develop accurate SPICE models from verified S-parameter measurements. By using an easy to follow, step by step procedure, this video walks you through the entire modeling flow for an on-wafer capacitor, using the Keysight Measurement and Modeling Software IC-CAP.

The IC-CAP project can be downloaded, together with a detailed How-to-Use description, and an in-depth tutorial about passive components modeling, applying the demonstrated method.

[VIDEO]

[ESSCIRC 2015] Low-power analog RF circuit design based on the inversion coefficient

[ref] Enz, Christian; Chalkiadaki, Maria-Anna; Mangla, Anurag, "Low-power analog/RF circuit design based on the inversion coefficient," in ESSCIRC 2015 - 41st , vol., no., pp.202-208, 14-18 Sept. 2015

Abstract: This paper discusses the concept of the inversion coefficient as an essential design parameter that spans the entire range of operating points from weak via moderate to strong inversion, including velocity saturation. Several figures-of-merit based on the inversion coefficient, especially suitable for the design of low-power analog and RF circuits, are presented. These figures-of-merit incorporate the various trade-offs encountered in analog and RF circuit design. The use of the inversion coefficient and the derived figures-of-merit for optimization and design is demonstrated through simple examples. Finally, the simplicity of the inversion coefficient based analytical models is emphasized by their favorable comparison against measurements of a commercial 40-nm bulk CMOS process as well as with simulations using the BSIM6 model.

Keywords: Analytical models, Integrated circuits, Noise, Radio frequency, Silicon, Transconductance, Transistors, BSIM6

URL / doi: 10.1109/ESSCIRC.2015.7313863

Call for IJNM papers: Noise modeling of high-frequency semiconductor devices

INTERNATIONAL JOURNAL OF NUMERICAL MODELLING: ELECTRONIC NETWORKS, DEVICES AND FIELDS Int. J. Numer. Model. (2014)

Call for IJNM papers: Noise modeling of high-frequency semiconductor devices 

Noise processes in solid-state active devices often determine their fundamental operational limits. This is especially true in situations where a device operates under tight sensitivity and accuracy constraints, as is the case in satellite communication systems, aerospace instrumentation, and deep-space radio astronomy. Today’s ultra-high frequency transistors that meet these demanding low-noise performance characteristics often leverage progressive device downscaling techniques in conjunction with improved semiconductor alloys. 

To enable the design of next-generation low-noise devices, however, accurate and flexible models that characterize the connection between the physics of microscopic noise processes and measurable macroscopic performance are called for. The objective of this Special Issue is to collect and disseminate recent results addressing the topic of modeling and simulation of the macroscopic noise performance of high- frequency transistors including but not limited to GaAs-based and GaN-based field-effect transistors, Si metal–oxide–semiconductor FETs and FinFETs, InP-based high-electron-mobility transistors, and GaAs and SiGe heterojunction bipolar transistors. It is worth pointing out that because of frequency up-conversion phenomena caused by a device’s nonlinearities, low frequency noise processes may strongly impact microwave and millimeter wave behavior as well. Contributions focusing on low-frequency noise modeling therefore will be considered as well. 

This issue will include both invited and contributed manuscripts.

Manuscripts for this Special Issue should adhere to the requirements for regular papers of the IJNM as specified in the Author Guidelines at 

http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1099-1204/ homepage/ForAuthors.html. 

Potential contributors may contact the Guest Editors to determine the suitability of their contribution to the Special Issue. All manuscripts should be submitted via the IJNM’s manuscript website, with a statement that they are intended for this Special Issue. 

Guest Editors: 
Prof. Alina Caddemi University of Messina, Italy Email:
Prof. Ernesto Limiti University of Rome Tor Vergata, Italy Email:

Manuscript submission deadline: July 31, 2014

13th HICUM Workshop 2013

HICUM Workshop at TU-Delft, May 27-28, 2013

The HIgh CUrrent Model (HICUM) has become an industry standard and one of the most suitable compact models for modern HBTs fabricated in latest process technologies covering a wide range of high frequency and mmW applications.

Since 2001, the annual HICUM Workshop has become a technical forum for the needs and interests of model users and developers for discussing the present trends and future needs of the bipolar transistor modeling and circuit design community.

Workshop Highlights:

• Special presentation by Prof. Spirito on mm-wave on-wafer measurements
• Various presentations covering the modeling of various bipolar transistor phenomena, new parameter extraction strategies, production-type model development, model testing and performance comparisons
• Special presentations on benchmark circuits for model verification (solicited)

Further queries? Contact: Anindya.Mukherjee@tu-dresden.de or Michael.Schroeter@tu-dresden.de

Call for IJNM Papers: Modeling of high-frequency silicon transistors

Silicon transistors (STs) have been the workhorse of the electronics industry ever since its inception. Although STs historically have been used primarily in digital and low-frequency analog applications, they increasingly are being adopted for high-frequency analog purposes as well. This trend is fueled by the introduction of new fabrication methods, novel materials, and transistor architectures that permit aggressive downscaling into the nanometer regime. Along these lines, considerable attention currently is being devoted to the FinFET, which is an innovative multiple-gate field effect transistor offering the important advantage of being compatible with conventional planar CMOS technology.

Modeling and simulation are indispensable in the development of high-frequency STs. Indeed, ST models and simulations provide indispensable feedback for improving device fabrication processes and serve as a valuable tool for optimizing circuit designs. Unfortunately, the predictive power of modeling and simulation techniques for STs for digital and low-frequency applications oftentimes diminishes when applied to high-frequency analog STs. For modeling and simulation methods to drive the development of high-frequency ST technology, they must adapt as well. 

The purpose of this Special Issue is to publish high-quality contributions addressing the modeling and simulation of high-frequency STs. A wide range of topics will be covered, ranging from bipolar to ?eld effect transistors and from linear to noise and non-linear models. Although the main focus of the Special Issue will be the extraction of high-frequency models, papers addressing other aspects of ST modeling will be considered as well. This issue will contain both invited and contributed papers. Manuscripts for this Special Issue should adhere to the requirements for regular papers of the IJNM as specified in the Author Guidelines at http://onlinelibrary.wiley.com/journal/10.1002/ (ISSN)1099-1204/homepage/ForAuthors.html.

Potential contributors may contact the Guest Editors to determine the suitability of their contribution to the Special Issue. All manuscripts should be submitted via the IJNM’s manuscript website http://mc.manuscriptcentral.com/ijnm, with a statement that they are intended for this Special Issue.

Guest Editors:

• Dr. Giovanni Crupi
  University of Messina, Italy
  E-mail: crupig@unime.it
• Prof. Dominique Schreurs
  University of Leuven, Belgium
  E-mail: dominique.schreurs@esat.kuleuven.be
• Prof. Alina Caddemi
  University of Messina, Italy
  E-mail: acaddemi@unime.it

Manuscript submission deadline: April 30, 2013

CMRF Workshop (at BCTM)

CMRF Workshop (at BCTM)
Wednesday October 3, 2012, in Portland, Oregon, USA

Session Chair: Colin McAndrew

As with previous years the Workshop on Compact Modeling for RF/Microwave Applications (CMRF) is being held in conjunction with BCTM. The workshop has an interactive dynamic, and this year includes a Forum of experts who will assess the present major needs in modeling.

1:00–1:30 PM – Advanced SiGe HBT Modeling with HICUM Level 0 (v1.3) for RF and mmW Applications
D. Celi and N. Derrier

This presentation deals with advanced bipolar modeling using the latest revision of HICUM/L0 (1.3). Following an overview of test structures and measurement setup used for bipolar transistors, the new HICUM/L0 formulations are described. Subsequently a workflow for parameter extraction is detailed that is suitable for advanced SiGe heterojunction bipolar transistors for mmW applications. As a last point the possibilities and limitations of the model and the parameter extraction are discussed.

1:30–2:00 PM – Dynamic Ageing Modeling for Reliability Simulation
B. Ardouin

Semiconductor device behavior is not static but changes over time, and the amount of change depends on details of the voltages and currents a device experiences. This presentation will review recent development of a dynamic ageing model for HiCuM 2.3 and provides details of Verilog-A implementation and pragmatic modeling issues related to self-consistent integration of transistor degradation in accelerated time based on realistic transient circuit operation.

2:00–2:30 PM – End-to-End Modeling for Handset Power Amplifiers – It’s Not Just Two Transistors!
P. Zampardi, Y. Yang, K. Kwok, B. Li, A. Metzger, C. Cismaru, H. Shao, W. Sun, and M. Fredriksson

The short design cycle for handset power amplifiers relies on accurate models for ALL components used in the design, not just the “two HBTs” used for the power transistors. As the complexity of these amplifiers (usually used in front-end modules) has increased, so has the required accuracy for simulating the package, control circuitry, and the RF chain itself. This presentation will show some of the challenges and solutions developed to address the development of high-yield commercial power amplifiers and the design flow for their realization.

2:50–3:20 PM – Practical Modeling: When Less is More
A. DiVergilio

The primary goal of compact modeling is to allow designs to be carried out quickly and efficiently. Therefore, model accuracy is not the only metric of model effectiveness. No matter what the circuit, significant portions of the design cycle can benefit more from rapid iteration than from absolute accuracy. Overly-complicated models slow down simulation and, at worst, prevent convergence all-together, especially for large designs. This presentation discusses trade-offs that can be made between speed and accuracy, emphasizing the flexibility that can be achieved through high-level modeling languages, such as Verilog-A, when applied to device-level model development.

3:20–4:20 PM – Forum: “Grand Challenges in Modeling”
Queen Marie Ballroom

Models are by definition imperfect, but what are the biggest opportunities for improvement that will have the biggest bang-for-the-buck in design? This forum will attempt to answer that question, and formulate a prioritized list of items that will be published on the BCTM web site.

Participants:

• Bertrand Ardouin (XMOD technologies)
• Adam DiVergilio (Tektronix)
• Mikhail Shirokov (Triquint Semiconductor)
• Peter Zampardi (Skyworks Solutions)
• Colin McAndrew (Moderator; Freescale)

April 14, 2009: ESSDERC/ESSCIRC submission deadlines

ESSDERC/ESSCIRC submission deadlines have been moved to April 14, 2009!

Visit the conference web site: http://www.essderc2009.org

after Analogschaltungen'09 in Hannover

The workshop program included following topics:

• Novel CMOS/BiCMOS circuit architectures for the GHz range applications
  
• Models of semiconductor devices for analog/RF (GHz range) applications
  
• Influences of the system design and optimization on the components in the analog circuit applications
• Classical and quantum mechanical effects in analog/RF nano-silicon circuits at GHz frequencies
  

The workshop has been organized by:

• Prof. Dr. -Ing. Wolfgang Mathis, Leibniz Universität Hannover, Institut für Theoretische Elektrotechnik; Appelstr. 9A, 30167 Hannover

in cooperation with:

• Prof. Dr.rer. nat. Doris Schmitt- Landsiedel, TU München; Lehrstuhl für Technische Elektronik
• Prof. Dr. -Ing. Heinrich Klar, TU Berlin; Institut für Technische Informatik und Mikroelektronik
• Prof. Dr.-Ing. Y. Manoli, Universität Freiburg; IMTEK