Latch-Up: a weekend of presentations and networking for the open source silicon community, much like its European sister conference ORConf.
Produced by NDV: @nextdayvideo
OpenHardware Sat Apr 20 16:20:00 2024 at b45r230
Holger Blume; Leibniz Universität Hannover & edacentrum e.V.14:15 Grußworte
Apollonia Pane Bundesministerium für Bildung und Forschung14:30 Vorstellung Chipdesign Germany
Holger Blume; Leibniz Universität Hannover & edacentrum e.V.14:45 Keynote-Session I
Norbert Wehn; Rheinland-Pfälzische Technische Universität Kaiserslautern-Landau
14:45 Open-Source EDA and Innovation Leadership
Andrew B. Kahng; University of California San Diego, US
16:30 Open Source Chip Design: Europas Weg zur Wettbewerbsfähigkeit in einer geteilten Tech-Welt?Jan-Peter Kleinhans; Stiftung Neue Verantwortung17:30 Mikroelektronik in digitalen Hörhilfen: Chips, die hören helfenJoachim Thiemann; Advanced Bionic
Holger Blume; Leibniz Universität Hannover & edacentrum e.V
Lutz Rissing; Dr. Johannes Heidenhain GmbH
BMBF-Förderlinie "Design-Instrumente für souveräne Chipentwicklung mit Open-Source (DE:Sign)"
10:30 DI-OCRCpro
Daniel Krupka; Gesellschaft für Informatik e.V.
10:45 DI-DEMICO
Frank Ellinger; Technische Universität Dresden
11:00 DI-DERAMSys
Matthias Jung; Julius-Maximilian-Universität Würzburg
11:15 DI-OWAS
Dirk Koch; Ruprecht-Karls-Universität Heidelberg
11:30 DI-PASSIONATE
Robert Weigel; Friedrich-Alexander Universität Erlangen-Nürnberg
Acknowledgements: The authors thank Johannes Kepler University for funding the open-access publication, Google and SkyWater Technologies for igniting this recent wave of open-source IC design, and the large crowd of enthusiasts spending their time on developing and maintaining an extensive array of exciting open-source EDA projects. Open access funding provided by Johannes Kepler University, Linz.
Friday, January 26, 2024, 18:00-21:00 (Reception: 18:30)
Google Shibuya Office
3-21-3 Shibuya, Shibuya-ku, Tokyo
Shibuya Stream Google reception meeting
Google Meet: https://meet.google.com/ksa-tjaw-ges
free
Time | Speaker | Title | Lecture Outline |
---|---|---|---|
Until 18:30 | ISHI-kai | reception | The entrance to the facility closes at this time, so if you are participating locally, please come by this time as much as possible. |
18:00 ~ 18:30 | ISHI-kai | Chat time | - |
18:30 ~ 19:15 (Lecture: 30min, Q&A: 15min) | Takeshi Hamamoto Minimal Fab Propulsion Organization Device Engineer | minimal Fab open PDK | 1) What is a minimal fab 2) openPDK 3) Design Contest at Semicon 2023 |
19:15 ~ 20:00 (Lecture: 30min., Q&A: 15min.) | Junichi Okamura IEEE Senior Member | OpenPDK and the World | - |
20:00 ~ 20:45 (Lecture: 30min., Q&A: 15min.) | @noritsuna | About the upcoming open source PDK shuttle | (To be released at a later date) |
21:00 | ISHI-kai | closing |
11:00 - 11:05 | Welcome |
11:05 - 11:10 | Introducing Open Source Silicon |
11:10 - 11:20 | BACKGROUND Open source silicon between software and hardware Background |
11:20 - 11:40 | POLICY BRIEF PRESENTATION Open source silicon’s position in the semiconductor value chain |
11:40 - 12:35 | PANEL Key opportunities and threats relevant to open source silicon strategies |
12:35 - 12:45 | Q&A and conclusions |
Laboratoire d'Informatique de Paris 6 (LIP6) Sorbonne and CNRS will attend Open Source Experience event on 6-7 December in Paris to present GoIT project
Come and join the European open source community meeting!!
[ read more... ]
Abstract: This paper presents a spiking neural network (SNN) accelerator made using fully open-source EDA tools, process design kit (PDK), and memory macros synthesized using Open- RAM. The chip is taped out in the 130 nm SkyWater process and integrates over 1 million synaptic weights, and offers a reprogrammable architecture. It operates at a clock speed of 40 MHz, a supply of 1.8 V, uses a PicoRV32 core for control, and occupies an area of 33.3 mm2. The throughput of the accelerator is 48,262 images per second with a wallclock time of 20.72 μs, at 56.8 GOPS/W. The spiking neurons use hysteresis to provide an adaptive threshold (i.e., a Schmitt trigger) which can reduce state instability. This results in high performing SNNs across a range of benchmarks that remain competitive with state-of-the-art, full precision SNNs.
The design is open sourced and available online: https://github.com/sfmth/OpenSpike
Roadmap: OpenVAF is still in development and there many goals we aim to achieve in the longterm:
Circuit simulators play a critical role in the design of electrical circuits. Accurate simulations enable circuit designers to validate circuit behavior before actual fabrication happens, potentially saving significant re-design costs. The simulation of a circuit critically depends on the so-called compact models and therefore:
Verilog-A has been developed to address these problems and has become the de-facto standard for developing and distributing compact models. It allows implementing compact models via a simulator independent and standardized language. Verilog-A compilers can translate these models to machine code and allow simulators to use these models without manually implementing them. Verilog-A enables: