Arbeitskreis Modellierung von Systemen und Parameterextraktion
Modeling of Systems and Parameter Extraction Working Group
10th International MOS-AK Workshop in the Silicon Valley
San Jose, CA, December 6, 2017
The MOS-AK Compact Modeling Association, a global compact/SPICE modeling and Verilog-A standardization forum, held its 10th consecutive, international compact/SPICE workshop in the USA. The event was hosted on Dec.6, 2017, by Cadence Design Systems in the Silicon Valley with is a perfect place to celebrate a decade of the MOS-AK activities in the USA. The technical program of the event was coordination by Larry Nagel, OEC (USA) and Andrei Vladimirescu, UCB (USA); ISEP (FR) representing the International MOS-AK Board of R&D Advisers. The workshop has received full industrial sponsorship by Cadence Design Systems (lead sponsor) and Keysight Technologies with technical program promotion provided by the IEEE EDS SC-SF Chapter, IJHSES as well as NEEDS of nanoHUB.org
The MOS-AK workshop was opened by Hany Elhak, Cadence Design Systems, who has welcomed all the attendees and shared Cadence view on the compact modeling and its importance in the TCAD/EDA modeling/design ecosystem. A group of 40+ international academic researchers and modeling engineers attended 13 technical compact modeling presentations covering full development chain from the nanoscaled technologies thru semiconductor devices modeling to advanced IC design support. The MOS-AK speakers have shared their latest perspectives on compact/SPICE modeling and Verilog-A standardization in the dynamically evolving semiconductor industry and academic R&D.
The event featured advanced technical presentations covering compact model development, implementation, deployment and standardization covering full engineering R&D chain: TCAD/processing, device modeling, transistor level IC design support. These contributions were delivered by leading academic and industrial experts, including:  J. Xie, Cadence: Verilog-A debug tool: AHDL Lint;  R. Radojcic et al. PDA: A Complete Learning-Based Semiconductor Parametric Testing and Device Modeling Ecosystem, from Probing to Simulation;  D. Celi, STM: Generation of HICUM/L2 and HICUM/L0 Geometry Scalable Model Libraries;  I. Radu, SOITEC: SOI technology platforms for 5G: opportunity of collaboration;  Mierzwinski et al. Keysight: An Overview of the HiSIM SOI/SOTB Compact Models;  A. Pashkovich and B. Tudor, SILVACO: Featured Circuit Simulation Using SMARTSPICE Compact Models and Verilog-A;  A. Asenov, Uni. Glasgow: Compact Model Requirements for TCAD Based DTCO;  D. Yakimets et al. imec: Enablement of compact models for ultra-scaled CMOS technologies;  G. Hills et al. Uni. Stanford: Rapid Co-optimization of Processing & Circuit Design to Overcome Carbon Nanotube Variations;  W. Grabinski, EDS DL, MOS-AK (EU): FOSS/H Tools for Compact Modeling;  D. Navarro et al. Uni Hiroshima: A Normally-on MOSFET Compact Model based on Surface Potential Description;  K.-W. Pieper, Infineon: Aging simulation with variation of several model parameters;  T. Nigam and A. Kerber, GLOBALFOUNDRIES: Reliability characterization of discrete devices and modeling circuit level ageing in advanced CMOS technologies. All the presentations are available online for download at <http://www.mos-ak.org/silicon_valley_2017/>. Selected best presentation will be recommended for further publication in the IJHSES.
The MOS-AK Modeling Working Group has various deliverables and initiatives including a book entitled "Open Source CAD Tools for Compact Modeling" and open Verilog-A model directory with supporting FOSS TCAD/EDA tools. The MOS-AK Association plans to continue its standardization efforts by organizing future compact modeling meetings, workshops and courses in Europe, USA and China throughout coming 2018 year, including:
About MOS-AK Association:
MOS-AK, an international compact modeling association primarily focused in Europe, to enable international compact modeling R&D exchange in the North/Latin Americas, EMEA and Asia/Pacific Regions. The MOS-AK Modeling Working Group plays a central role in developing a common information exchange system among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact/SPICE modeling and its Verilog-A standardization and related CAD/EDA tools including FOSS for the compact/SPICE models development, validation/implementation and distribution. For more information please visit: mos-ak.org
About Cadence Design Systems:
Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play. Our products are used in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. For more information please visit: https://www.cadence.com
About Keysight Technologies
Keysight Technologies, Inc. (NYSE: KEYS) is a leading technology company that helps its engineering, enterprise and service provider customers accelerate innovation to connect and secure the world. Keysight's solutions optimize networks and bring electronic products to market faster and at a lower cost with offerings from design simulation, to prototype validation, to manufacturing test, to optimization in networks and cloud environments. Customers span the worldwide communications ecosystem, aerospace and defense, automotive, energy, semiconductor and general electronics end markets. Keysight generated revenues of $3.2B in fiscal year 2017. In April 2017, Keysight acquired Ixia, a leader in network test, visibility, and security. More information is available at www.keysight.com
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